https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127073
Bug ID: 127073
Summary: Missed LLVM's or disjoint detection for RISC-V
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: kaelfandrew at gmail dot com
Target Milestone: ---
https://godbolt.org/z/3qrMrvTEc
```
#define TYPE unsigned char
TYPE
src_add (TYPE x, TYPE y)
{
if ((x & y) != 0)
__builtin_unreachable ();
return (x + y);
}
TYPE
tgt_or (TYPE x, TYPE y)
{
if ((x & y) != 0)
__builtin_unreachable ();
return (x | y);
}
TYPE
tgt_xor (TYPE x, TYPE y)
{
if ((x & y) != 0)
__builtin_unreachable ();
return (x ^ y);
}
```
RISC-V 64 bit -O2 assembly:
```
src_add:
add a0,a0,a1
andi a0,a0,0xff
ret
tgt_or:
or a0,a0,a1
ret
tgt_xor:
xor a0,a0,a1
ret
```
src_add should optimize to one of
{or,and,xor} a0,a0,a1
ret
