https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102055
--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Pengxuan Zheng <[email protected]>: https://gcc.gnu.org/g:4182cf11e1e3d2ebcf4f5c3dff157f844a635bf8 commit r17-3712-g4182cf11e1e3d2ebcf4f5c3dff157f844a635bf8 Author: Pengxuan Zheng <[email protected]> Date: Wed Aug 26 18:20:21 2026 -0700 aarch64: Recognize vector permute patterns which can be optimized as REV64+EXT [PR102055] Currently, with Advanced SIMD vector char f (vector char a) { return __builtin_shuffle (a, (vector char){ 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 }); } generates: f: adrp x0, .LANCHOR0 ldr q31, [x0, #:lo12:.LANCHOR0] tbl v0.16b, {v0.16b}, v31.16b ret .set .LANCHOR0,. + 0 .LC0: .byte 15 .byte 14 .byte 13 .byte 12 .byte 11 .byte 10 .byte 9 .byte 8 .byte 7 .byte 6 .byte 5 .byte 4 .byte 3 .byte 2 .byte 1 .byte 0 With this patch, it generates REV64 followed by EXT: f: rev64 v0.16b, v0.16b ext v0.16b, v0.16b, v0.16b, #8 ret Bootstrapped and tested on aarch64_linux_gnu. Changes since v1: * v2: Add loop check to avoid generating REV64+EXT if the shuffle is inside a loop. PR target/102055 gcc/ChangeLog: * config/aarch64/aarch64.cc (is_bb_in_loop): New. (aarch64_evpc_rev64_ext): New. (aarch64_expand_vec_perm_const_1): Call aarch64_evpc_rev64_ext. gcc/testsuite/ChangeLog: * gcc.target/aarch64/pr102055-loop.c: New test. * gcc.target/aarch64/pr102055.c: New test. Signed-off-by: Pengxuan Zheng <[email protected]>
