https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127205
--- Comment #4 from Pengfei Li <pfustc at gcc dot gnu.org> ---
I've attached a reduced testcase from 549.fotonik3d_r.
Before the patches, the innermost loop has many post-indexed ldp/stp
instructions like
ldp qM, qN, [xPointer], #32
, which can load/store 32 bytes once and bump the pointer at the same time.
As larger IV sets are preferred after the patch, ivopts turned to use different
bases and a shared offset for the addressing. At a result, many separate
loads/stores like
ldr qM, [xBase1, x0]
ldr qN, [xBase2, x0]
together with an offset update instruction like
add x0, x0, 32
are generated. That's why more IVs do not necessarily mean less computations.
After the patches, we can also see much more spillings if a larger IV sets is
selected. All these result in much more instructions in the hot loop and worse
performance.
