https://gcc.gnu.org/bugzilla/show_bug.cgi?id=126196
--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The releases/gcc-16 branch has been updated by Jeff Law <[email protected]>: https://gcc.gnu.org/g:c457a158598614cc05abc46ce154c370b15628ef commit r16-9638-gc457a158598614cc05abc46ce154c370b15628ef Author: Jin Ma <[email protected]> Date: Sat Sep 5 10:07:33 2026 -0600 [PATCH v2] RISC-V: Fix overlapping vd/vs2 allocation for vector crypto [PR126196] The RISC-V Vector Crypto specification reserves encodings where the vd register group overlaps vs2 for vsm3me.vv, vsm3c.vi, vaes*.vs and vsm4r.vs. It also reserves encodings where vd overlaps either vs1 or vs2 for vsha2ms.vv, vsha2ch.vv and vsha2cl.vv. Use early-clobber destination constraints for the affected patterns. Select those constraints by UNSPEC where patterns are shared, keeping legal overlap for vghsh.vv, vaeskf2.vi, vgmul.vv and the .vv forms of AES and SM4. PR target/126196 gcc/ChangeLog: * config/riscv/vector-crypto.md (vv_ins_con): New int attribute. (vv_ins1_con): Likewise. (vi_ins1_con): Likewise. (@pred_v<vv_ins1_name><mode>): Use vv_ins1_con. (@pred_crypto_vv<vv_ins_name><ins_type><mode>): Use vv_ins_con. (@pred_vi<vi_ins1_name><mode>_nomaskedoff_scalar): Use vi_ins1_con. (@pred_vsm3me<mode>): Mark the destination as early-clobber. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr126196-1.c: New test. * gcc.target/riscv/pr126196-2.c: New test. * gcc.target/riscv/pr126196-3.c: New test. * gcc.target/riscv/pr126196-4.c: New test. (cherry picked from commit 7e88b4e76418b131268802ccba5f74cf1835fc66)
