[Bug tree-optimization/127216] [17 Regression] Vector averaging code gen regression after recent change

[liuhongt at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127216

--- Comment #2 from Hongtao Liu <liuhongt at gcc dot gnu.org> ---
This patch extend the existed avg_{floor,ceil} to the missed mode in the
regressed testcase, and should solve the issue?

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 16d08cae30b..eb8faf8e0ee 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2554,29 +2554,12 @@ (define_expand "len_fold_extract_last_<mode>"
 ;;  op[0] = (narrow) ((wide) op[1] + (wide) op[2] + 1)) >> 1;
 ;; -------------------------------------------------------------------------

-(define_expand "avg<v_double_trunc>3_floor"
- [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand")
-   (truncate:<V_DOUBLE_TRUNC>
-    (ashiftrt:VWEXTI
-     (plus:VWEXTI
-      (sign_extend:VWEXTI
-       (match_operand:<V_DOUBLE_TRUNC> 1 "register_operand"))
-      (sign_extend:VWEXTI
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 16d08cae30b..eb8faf8e0ee 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2554,29 +2554,12 @@ (define_expand "len_fold_extract_last_<mode>"
 ;;  op[0] = (narrow) ((wide) op[1] + (wide) op[2] + 1)) >> 1;
 ;; -------------------------------------------------------------------------

-(define_expand "avg<v_double_trunc>3_floor"
- [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand")
-   (truncate:<V_DOUBLE_TRUNC>
-    (ashiftrt:VWEXTI
-     (plus:VWEXTI
-      (sign_extend:VWEXTI
-       (match_operand:<V_DOUBLE_TRUNC> 1 "register_operand"))
-      (sign_extend:VWEXTI
-       (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand")))
-     (const_int 1))))]
-  "TARGET_VECTOR"
-  {
-    insn_code icode = code_for_pred (UNSPEC_VAADD, <V_DOUBLE_TRUNC>mode);
-    riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP_VXRM_RDN,
-                                  operands);
-    DONE;
-  }
-)
-
+;; csrwi vxrm, 2
+;; vaadd.vv vd, vs2, vs1
 (define_expand "avg<mode>3_floor"
- [(match_operand:V_VLSI_D 0 "register_operand")
-  (match_operand:V_VLSI_D 1 "register_operand")
-  (match_operand:V_VLSI_D 2 "register_operand")]
+ [(match_operand:V_VLSI 0 "register_operand")
+  (match_operand:V_VLSI 1 "register_operand")
+  (match_operand:V_VLSI 2 "register_operand")]
   "TARGET_VECTOR"
   {
     insn_code icode = code_for_pred (UNSPEC_VAADD, <MODE>mode);
@@ -2586,31 +2569,12 @@ (define_expand "avg<mode>3_floor"
   }
 )

-(define_expand "avg<v_double_trunc>3_ceil"
- [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand")
-   (truncate:<V_DOUBLE_TRUNC>
-    (ashiftrt:VWEXTI
-     (plus:VWEXTI
-      (plus:VWEXTI
-       (sign_extend:VWEXTI
-       (match_operand:<V_DOUBLE_TRUNC> 1 "register_operand"))
-       (sign_extend:VWEXTI
-       (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand")))
-      (const_int 1))
-     (const_int 1))))]
-  "TARGET_VECTOR"
-  {
-    insn_code icode = code_for_pred (UNSPEC_VAADD, <V_DOUBLE_TRUNC>mode);
-    riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP_VXRM_RNU,
-                                  operands);
-    DONE;
-  }
-)
-
+;; csrwi vxrm, 0
+;; vaadd.vv vd, vs2, vs1
 (define_expand "avg<mode>3_ceil"
- [(match_operand:V_VLSI_D 0 "register_operand")
-  (match_operand:V_VLSI_D 1 "register_operand")
-  (match_operand:V_VLSI_D 2 "register_operand")]
+ [(match_operand:V_VLSI 0 "register_operand")
+  (match_operand:V_VLSI 1 "register_operand")
+  (match_operand:V_VLSI 2 "register_operand")]
   "TARGET_VECTOR"
   {
     insn_code icode = code_for_pred (UNSPEC_VAADD, <MODE>mode);