[Bug target/127269] [17 Regression] [RISC-V] ICE in riscv_v_widen_constraint_ok during IRA pass with -march=rv64gcv

[pan2.li at intel dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127269

--- Comment #2 from Li Pan <pan2.li at intel dot com> ---
(In reply to Robin Dapp from comment #1)
> Confirmed.  Pan, could you have a look?

Ack and reproduced.