https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127677
Bug ID: 127677
Summary: Wrong code generated with VLS mode
(-mrvv-vector-bits=zvl)
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: middle-end
Assignee: unassigned at gcc dot gnu.org
Reporter: anton at ozlabs dot org
CC: tamar.christina at arm dot com
Target Milestone: ---
Created attachment 65726
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=65726&action=edit
Testcase
I am seeing miscompilation of both cpu2017 gcc and xalancbmk on RISC-V when
using -mrvv-vector-bits=zvl. I used AI to help create a cut down test case
(attached), hopefully it reproduces the issues I'm seeing.
riscv64-unknown-linux-gnu-gcc -O3 -march=rv64gcv_zvl256b -mabi=lp64d
-mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -static contains.c
qemu-riscv64 -cpu tt-ascalon ./a.out
Good SHA:
./a.out
519435 tests, 0 mismatches
First bad SHA: 8af2e8e49d6e5d33c01c2beaead4933bc286974c (vect: Don't generate
scalar epilogue if not needed [PR120352])
./a.out
MISMATCH count=1 start=0 key_pos=1 vec=1 ref=0
MISMATCH count=1 start=0 key_pos=2 vec=1 ref=0
MISMATCH count=1 start=0 key_pos=3 vec=1 ref=0
MISMATCH count=1 start=0 key_pos=4 vec=1 ref=0
MISMATCH count=1 start=0 key_pos=5 vec=1 ref=0
MISMATCH count=1 start=0 key_pos=6 vec=1 ref=0
MISMATCH count=1 start=0 key_pos=7 vec=1 ref=0
MISMATCH count=1 start=0 key_pos=8 vec=1 ref=0
MISMATCH count=1 start=0 key_pos=9 vec=1 ref=0
MISMATCH count=1 start=0 key_pos=10 vec=1 ref=0
499065 tests, 29309 mismatches
