https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127686
Bug ID: 127686
Summary: [17 Regression] 300% slowdown of vect-tsvc-s331.c
since r17-4622-gbbf9808d787eac (adding SSE to integer
move cost)
Product: gcc
Version: 17.0
Status: UNCONFIRMED
Keywords: missed-optimization
Severity: normal
Priority: P3
Component: tree-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: pheeck at gcc dot gnu.org
CC: rguenth at gcc dot gnu.org
Blocks: 116773
Target Milestone: ---
Host: x86_64-pc-linux-gnu
Target: x86_64-pc-linux-gnu
Happens across various x86_64 CPUs
https://lnt.opensuse.org/db_default/v4/CPP/graph?plot.0=176.911.0
https://lnt.opensuse.org/db_default/v4/CPP/graph?plot.0=466.911.0
https://lnt.opensuse.org/db_default/v4/CPP/graph?plot.0=286.911.0
https://lnt.opensuse.org/db_default/v4/CPP/graph?plot.0=556.911.0
https://lnt.opensuse.org/db_default/v4/CPP/graph?plot.0=994.911.0
Worst I've seen is a 300% slowdown on AMD Zen2. Compile
gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s331.c with -O2, but change the
'iterations' macro in gcc/testsuite/gcc.dg/vect/tsvc/tsvc.h to 10000. Run the
binary.
gcc -O2 vect-tsvc-s331.c -o vect-tsvc
time ./vect-tsvc
r17-4622-gbbf9808d787eac
real 0m0.424s
user 0m0.421s
sys 0m0.003s
r17-4621-gd6ca7e8e1cf627
real 0m0.095s
user 0m0.092s
sys 0m0.004s
commit bbf9808d787eacf4464f2298d2f4265855b006bf
Author: Richard Biener <[email protected]>
AuthorDate: Wed Sep 23 11:04:39 2026 +0200
Commit: Richard Biener <[email protected]>
CommitDate: Thu Sep 24 09:14:22 2026 +0200
account for SSE to integer move cost for vec_to_scalar
vec_to_scalar costs a lane extraction which might be lane zero
from a vector to a scalar. The following makes us account for
the extra cost when the target is a GPR.
I chose to not limit the testcase to any tuning/ISA, it shouldn't
be vectorized for any combination.
PR target/127268
* config/i386/i386.cc (ix86_default_vector_cost): For
integer mode vec_to_scalar add sse_to_integer cost.
* gcc.target/i386/vect-bb-reduc-1.c: New testcase.
Here is objdump -d of the s331 function
r17-4622-gbbf9808d787eac
------------------------
00000000004074f0 <s331>:
4074f0: 55 push %rbp
4074f1: bf b5 85 40 00 mov $0x4085b5,%edi
4074f6: bd 10 27 00 00 mov $0x2710,%ebp
4074fb: 53 push %rbx
4074fc: 48 83 ec 08 sub $0x8,%rsp
407500: e8 2b a7 ff ff call 401c30 <initialise_arrays>
407505: 66 0f ef c9 pxor %xmm1,%xmm1
407509: 31 c0 xor %eax,%eax
40750b: bb ff ff ff ff mov $0xffffffff,%ebx
407510: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1)
407515: 66 66 2e 0f 1f 84 00 data16 cs nopw 0x0(%rax,%rax,1)
40751c: 00 00 00 00
407520: 0f 2e 0c 85 00 65 5a ucomiss 0x5a6500(,%rax,4),%xmm1
407527: 00
407528: 0f 47 d8 cmova %eax,%ebx
40752b: 48 83 c0 01 add $0x1,%rax
40752f: 48 3d 00 7d 00 00 cmp $0x7d00,%rax
407535: 75 e9 jne 407520 <s331+0x30>
407537: 66 0f ef c0 pxor %xmm0,%xmm0
40753b: 68 00 95 46 00 push $0x469500
407540: ba 00 7d 56 00 mov $0x567d00,%edx
407545: 41 b9 00 95 4e 00 mov $0x4e9500,%r9d
40754b: f3 0f 2a c3 cvtsi2ss %ebx,%xmm0
40754f: 68 00 95 4a 00 push $0x4a9500
407554: 41 b8 00 95 52 00 mov $0x529500,%r8d
40755a: b9 00 89 54 00 mov $0x548900,%ecx
40755f: be 00 71 58 00 mov $0x587100,%esi
407564: bf 00 65 5a 00 mov $0x5a6500,%edi
407569: e8 72 ff ff ff call 4074e0 <dummy>
40756e: 83 ed 01 sub $0x1,%ebp
407571: 58 pop %rax
407572: 66 0f ef c9 pxor %xmm1,%xmm1
407576: 5a pop %rdx
407577: 75 90 jne 407509 <s331+0x19>
407579: 83 c3 01 add $0x1,%ebx
40757c: 48 83 c4 08 add $0x8,%rsp
407580: 66 0f ef c0 pxor %xmm0,%xmm0
407584: f3 0f 2a c3 cvtsi2ss %ebx,%xmm0
407588: 5b pop %rbx
407589: 5d pop %rbp
40758a: c3 ret
r17-4621-gd6ca7e8e1cf627
------------------------
00000000004074f0 <s331>:
4074f0: 55 push %rbp
4074f1: bf b5 85 40 00 mov $0x4085b5,%edi
4074f6: bd 10 27 00 00 mov $0x2710,%ebp
4074fb: 53 push %rbx
4074fc: 48 83 ec 08 sub $0x8,%rsp
407500: e8 2b a7 ff ff call 401c30 <initialise_arrays>
407505: b8 04 00 00 00 mov $0x4,%eax
40750a: 66 0f ef ed pxor %xmm5,%xmm5
40750e: 66 0f 6e e0 movd %eax,%xmm4
407512: 66 0f 70 e4 00 pshufd $0x0,%xmm4,%xmm4
407517: 66 0f 6f 0d a1 10 00 movdqa 0x10a1(%rip),%xmm1 #
4085c0 <__func__.0+0xb>
40751e: 00
40751f: b8 00 65 5a 00 mov $0x5a6500,%eax
407524: 66 0f 76 d2 pcmpeqd %xmm2,%xmm2
407528: 66 90 xchg %ax,%ax
40752a: 66 66 2e 0f 1f 84 00 data16 cs nopw 0x0(%rax,%rax,1)
407531: 00 00 00 00
407535: 66 66 2e 0f 1f 84 00 data16 cs nopw 0x0(%rax,%rax,1)
40753c: 00 00 00 00
407540: 0f 28 00 movaps (%rax),%xmm0
407543: 66 0f 6f d9 movdqa %xmm1,%xmm3
407547: 48 83 c0 10 add $0x10,%rax
40754b: 66 0f fe cc paddd %xmm4,%xmm1
40754f: 0f c2 c5 01 cmpltps %xmm5,%xmm0
407553: 66 0f db d8 pand %xmm0,%xmm3
407557: 66 0f df c2 pandn %xmm2,%xmm0
40755b: 66 0f 6f d0 movdqa %xmm0,%xmm2
40755f: 66 0f eb d3 por %xmm3,%xmm2
407563: 48 3d 00 59 5c 00 cmp $0x5c5900,%rax
407569: 75 d5 jne 407540 <s331+0x50>
40756b: 66 0f 6f c2 movdqa %xmm2,%xmm0
40756f: 68 00 95 46 00 push $0x469500
407574: ba 00 7d 56 00 mov $0x567d00,%edx
407579: 41 b9 00 95 4e 00 mov $0x4e9500,%r9d
40757f: 66 0f 73 d8 08 psrldq $0x8,%xmm0
407584: 68 00 95 4a 00 push $0x4a9500
407589: 41 b8 00 95 52 00 mov $0x529500,%r8d
40758f: b9 00 89 54 00 mov $0x548900,%ecx
407594: 66 0f 6f c8 movdqa %xmm0,%xmm1
407598: be 00 71 58 00 mov $0x587100,%esi
40759d: bf 00 65 5a 00 mov $0x5a6500,%edi
4075a2: 66 0f 66 ca pcmpgtd %xmm2,%xmm1
4075a6: 66 0f db c1 pand %xmm1,%xmm0
4075aa: 66 0f df ca pandn %xmm2,%xmm1
4075ae: 66 0f eb c8 por %xmm0,%xmm1
4075b2: 66 0f 6f d1 movdqa %xmm1,%xmm2
4075b6: 66 0f 73 da 04 psrldq $0x4,%xmm2
4075bb: 66 0f 6f c2 movdqa %xmm2,%xmm0
4075bf: 66 0f 66 c1 pcmpgtd %xmm1,%xmm0
4075c3: 66 0f db d0 pand %xmm0,%xmm2
4075c7: 66 0f df c1 pandn %xmm1,%xmm0
4075cb: 66 0f eb c2 por %xmm2,%xmm0
4075cf: 66 0f 7e c3 movd %xmm0,%ebx
4075d3: 66 0f ef c0 pxor %xmm0,%xmm0
4075d7: f3 0f 2a c3 cvtsi2ss %ebx,%xmm0
4075db: e8 00 ff ff ff call 4074e0 <dummy>
4075e0: 83 ed 01 sub $0x1,%ebp
4075e3: 58 pop %rax
4075e4: 66 0f ef ed pxor %xmm5,%xmm5
4075e8: 66 0f 6f 25 e0 0f 00 movdqa 0xfe0(%rip),%xmm4 #
4085d0 <__func__.0+0x1b>
4075ef: 00
4075f0: 5a pop %rdx
4075f1: 0f 85 20 ff ff ff jne 407517 <s331+0x27>
4075f7: 83 c3 01 add $0x1,%ebx
4075fa: 48 83 c4 08 add $0x8,%rsp
4075fe: 66 0f ef c0 pxor %xmm0,%xmm0
407602: f3 0f 2a c3 cvtsi2ss %ebx,%xmm0
407606: 5b pop %rbx
407607: 5d pop %rbp
407608: c3 ret
Referenced Bugs:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116773
[Bug 116773] [meta-bug] TSVC missed optimizations
