https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108477
--- Comment #7 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Roger Sayle <[email protected]>: https://gcc.gnu.org/g:415316f432cd03755735f13f226d5193785ea8a9 commit r17-5043-g415316f432cd03755735f13f226d5193785ea8a9 Author: Roger Sayle <[email protected]> Date: Fri Oct 9 22:07:34 2026 +0100 AArch64: Change the bitfield patterns to be any-or-plus (AOP) safe. This patch tweaks aarch64.md's buitfield patterns to be more AOP-safe, i.e. can recognize bfi, bfxil and rev16 instructions when expressed in RTL using either PLUS, IOR or XOR. The recent PR tree-optimization/108477 patch caused 8 testsuite regressions on aarch64, and this patch addresses the machine description issues and resolves 2 of those 8 FAILs. Firstly, many thanks to Kyrill Tkachov for reviewing/approving the previous aarch64 fix for AOP issues (around movk). https://gcc.gnu.org/pipermail/gcc-patches/2026-September/729755.html For PR 108477, the middle-end is now even more aggressively select between PLUS and IOR, by making use of get_nonzero_bits during expand. Alas on aarch64 this causes the following code quality (not correctness) regressions in the testsuite: FAIL: gcc.target/aarch64/combine_bfi_1.c scan-assembler-times \\tbfi\\t 5 FAIL: gcc.target/aarch64/combine_bfi_2.c scan-assembler-times \\tbfi\\t 2 FAIL: gcc.target/aarch64/combine_bfxil.c scan-assembler-times bfxil\\t 3 FAIL: gcc.target/aarch64/combine_bfxil.c scan-assembler-times bfi\\t 15 FAIL: gcc.target/aarch64/fcvt_int_float_double3.c scan-assembler \\tscvtf\\td0, w[0-9]* FAIL: gcc.target/aarch64/movk_2.c check-function-bodies f2 FAIL: gcc.target/aarch64/pr100028.c scan-assembler-times \\tbfxil\\t 2 FAIL: gcc.target/aarch64/rev16_2.c scan-assembler-times rev16\\tx[0-9]+ 2 I'd initially hoped this patch would be sufficient to avoid these regressions, but alas providing AOP-safe patterns only allows combine to "recognize" these instructions, but (for the first six above) aarch64_rtx_costs also needs to provide accurate estimates for them to be used. It turns out the cost infrastructure is (partially) shared with the arm backend (via aarch-common), and my patch to the upstream config/arm/aarch-common.cc is still awaiting review. https://gcc.gnu.org/pipermail/gcc-patches/2026-September/732926.html 2026-10-09 Roger Sayle <[email protected]> gcc/ChangeLog * config/aarch64/aarch64.cc (aarch64_extr_rtx_p): Allow extr pattern to be represented as either IOR, XOR or PLUS. * config/aarch64/aarch64.md (*aarch64_bfxil<mode>_extr): Use any_or_plus iterator. (*aarch64_bfxilsi_extrdi): Likewise. (*aarch64_bfxil<mode>): Likewise. (*aarch64_bfxilsi_uxtw): Likewise. (aarch64_rev16<mode>2_alt1): Use any_or_plus iterator and new aop_pref_ior attribute so that the gen function uses IOR. (*aarch64_rev16<mode>2_alt2): Use any_or_plus iterator. (*aarch64_rev16si2_alt3): Add "*" prefix to skip gen function. * config/aarch64/iterators.md (aop_pref_ior): New code attribute to produce "*" for XOR/PLUS.
