[Bug rtl-optimization/127367] [15/16/17 Regression] RISC-V: wrong code for unsigned _BitInt(96) %

[sjames at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=127367

Sam James <sjames at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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   Target Milestone|17.0                        |15.3