[Bug rtl-optimization/128063] `op0 != 0 ? op0 & op1 : 0` can be optimized to just `op0 & op1` in RTL

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=128063

Drea Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|aarch64 x86_64              |aarch64 x86_64 riscv

--- Comment #1 from Drea Pinski <pinskia at gcc dot gnu.org> ---
This shows up on rv64gcb_zicond too.
For f:
```
Trying 35 -> 37:
   35: r144:DI=r136:DI&r140:DI
      REG_DEAD r140:DI
   37: r147:DI={(r136:DI==0)?0:r144:DI}
      REG_DEAD r144:DI
      REG_DEAD r136:DI
Failed to match this instruction:
(set (reg:DI 147)
    (if_then_else:DI (ne:DI (reg/v:DI 136 [ aD.2468 ])
            (const_int 0 [0]))
        (and:DI (reg/v:DI 136 [ aD.2468 ])
            (reg:DI 140))
        (const_int 0 [0])))
```

f1 is slightly more complex though:
```
Trying 32, 33 -> 35:
   32: r140:DI=r135:DI&r137:DI
      REG_DEAD r135:DI
   33: r143:DI=sign_extend(r140:DI#0)
      REG_DEAD r140:DI
   35: r146:DI={(r137:DI==0)?0:r143:DI}
      REG_DEAD r143:DI
      REG_DEAD r137:DI
Failed to match this instruction:
(set (reg:DI 146)
    (if_then_else:DI (ne:DI (reg/v:DI 137 [ aD.2473 ])
            (const_int 0 [0]))
        (sign_extend:DI (subreg:SI (and:DI (reg:DI 135 [ _2 ])
                    (reg/v:DI 137 [ aD.2473 ])) 0))
        (const_int 0 [0])))
```