https://gcc.gnu.org/g:22e30d60b971eed9a4754ea920d05b1b7e89090a
commit r15-7451-g22e30d60b971eed9a4754ea920d05b1b7e89090a
Author: Jeff Law <j...@ventanamicro.com>
Date: Sun Feb 9 09:55:56 2025 -0700
[PR target/115123] Fix testsuite fallout from sinking heuristic change
Code sinking is just semantic preserving code motions, so it's a lot like
scheduling in that code motions can change the vector configuration needed
at
various program points. That in turn can also change the number of vsetvls
as
we may or may not be able to merge them after the code motions.
The sinking heuristics were twiddled several months ago resulting in a
handful
of scan-asm failures. This patch adjusts the tests appropriately fixing
pr115123 (P3 regression).
PR target/115123
gcc/testsuite
* gcc.target/riscv/rvv/base/pr114352-3.c: Adjust expected output.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/avl_single-66.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/avl_single-82.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/avl_single-83.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/avl_single-86.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/avl_single-88.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/avl_single-90.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/avl_single-91.c: Likewise.
* gcc.target/riscv/rvv/vsetvl/avl_single-92.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c | 1 -
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c | 1 -
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c | 1 -
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c | 1 -
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c | 4 ++--
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c | 2 +-
11 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
index a764afbbbc19..9bfa39c52680 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
@@ -4,6 +4,7 @@
/*
** test_1:
+** ...
** sext\.w\s+[atx][0-9]+,\s*[atx][0-9]+
** ...
*/
@@ -56,6 +57,7 @@ test_3 (int *a, int *b, int *out, unsigned count)
/*
** test_4:
+** ...
** sext\.w\s+[atx][0-9]+,\s*[atx][0-9]+
** ...
*/
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c
index 21bc0729cf68..cdb1a4ee921f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int l, int
n, int m, int cond)
}
}
-/* { dg-final { scan-assembler
{add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+ble\s+[a-x0-9]+,\s*zero,\.L[0-9]+\s+vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]}
{ target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler
{add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+ble\s+[a-x0-9]+,\s*zero,\.L[0-9]+\s+.L[0-9]+:\s+vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]}
{ target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c
index 5539486b5060..c7c9e1f91ffe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c
@@ -36,4 +36,4 @@ void f (void * restrict in, void * restrict out, int l, int
n, int m, int cond)
}
}
-/* { dg-final { scan-assembler
{add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+ble\s+[a-x0-9]+,\s*zero,\.L[0-9]+\s+vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]}
{ target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler
{add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+ble\s+[a-x0-9]+,\s*zero,\.L[0-9]+\s+.L[0-9]+:\s+vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]}
{ target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
index 6e995461c6f7..c174845f7bc6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-66.c
@@ -17,5 +17,4 @@ void f2 (void * restrict in, void * restrict out, int l, int
n, int m, size_t vl
}
}
-/* { dg-final { scan-assembler-times
{add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+ble\s+[a-x0-9]+,\s*zero,\.L[0-9]+\s+}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-g" no-opts "-funroll-loops" } } } } */
/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
no-opts "-g" no-opts "-funroll-loops" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c
index 707bedadae0d..474116378c08 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-82.c
@@ -24,7 +24,7 @@ float f0 (int8_t * restrict in, int8_t * restrict out, int n,
int m, unsigned co
return __riscv_vfmv_f_s_f32m1_f32 (v);
}
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts
"-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts
"-funroll-loops" } } } } */
/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0"
no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops"
} } } } */
/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops"
} } } } */
-/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops"
} } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 2 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops"
} } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c
index 6e64712074e3..e8135f45e78a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-83.c
@@ -25,7 +25,7 @@ float f0 (int8_t * restrict in, int8_t * restrict out, int n,
int m, unsigned co
return __riscv_vfmv_f_s_f32m1_f32 (v);
}
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts
"-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts
"-funroll-loops" } } } } */
/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0"
no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops"
} } } } */
/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops"
} } } } */
-/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops"
} } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 2 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops"
} } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c
index 14b934acaab9..a1bba4c9763e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-86.c
@@ -26,4 +26,3 @@ float f1 (int8_t * restrict in, int8_t * restrict out, int n,
int m, unsigned co
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts
"-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts
"-funroll-loops" } } } } */
/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops"
} } } } */
-/* { dg-final { scan-assembler-not {vsetivli} { target { no-opts "-O0" no-opts
"-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } }
*/
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c
index c98dbdc7a06c..6f765e4cde4c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-88.c
@@ -26,4 +26,3 @@ float f (int8_t * restrict in, int8_t * restrict out, int n,
int m, unsigned con
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts
"-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts
"-funroll-loops" } } } } */
/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops"
} } } } */
-/* { dg-final { scan-assembler-not {vsetivli} { target { no-opts "-O0" no-opts
"-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } }
*/
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c
index 82db207850ee..788c77062516 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-90.c
@@ -27,4 +27,3 @@ float f2 (int8_t * restrict in, int8_t * restrict out, int n,
int m, unsigned co
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts
"-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts
"-funroll-loops" } } } } */
/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops"
} } } } */
-/* { dg-final { scan-assembler-not {vsetivli} { target { no-opts "-O0" no-opts
"-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } }
*/
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c
index d8b5d6f57cde..363d9b12b2be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-91.c
@@ -27,7 +27,7 @@ float f3 (int8_t * restrict in, int8_t * restrict out, int n,
int m, unsigned co
/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*3,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts
"-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts
"-funroll-loops" } } } } */
/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*3,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts
"-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts
"-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts
"-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts
"-funroll-loops" } } } } */
/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts
"-funroll-loops" } } } } */
/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops"
} } } } */
-/* { dg-final { scan-assembler-times {vsetivli} 2 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops"
} } } } */
+/* { dg-final { scan-assembler-times {vsetivli} 3 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops"
} } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c
index d4ab9f561f81..57b0ca150afe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-92.c
@@ -21,6 +21,6 @@ float f (int8_t * restrict in, int8_t * restrict out, int n,
int m, unsigned con
}
/* { dg-final { scan-assembler-times
{vsetivli\s+zero,\s*3,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts
"-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts
"-funroll-loops" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts
"-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts
"-funroll-loops" } } } } */
/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops"
} } } } */
/* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops"
} } } } */
