https://gcc.gnu.org/g:b3dee815f2beb48c5bd7c5309cd8652446720499
commit b3dee815f2beb48c5bd7c5309cd8652446720499 Author: Michael Meissner <[email protected]> Date: Tue Sep 9 16:39:39 2025 -0400 Attempt to fix bfloat16 problems. 2025-09-09 Michael Meissner <[email protected]> gcc/ * config/rs6000/rs6000.cc (rs6000_option_override_internal): Require -mbfloat16 to use -mcpu=power10. * config/rs6000/rs6000.h (FP16_SCALAR_P): Drop TARGET_POWER10 check. * config/rs6000/rs6000.md (FP16): Add TARGET_IEEE16 and TARGET_BFLOAT16 checks. (mov<mode>, FP16 iterator): Drop FP16_SCALAR_P check. (mov<mode>_xxspltiw): Likewise. (mov<mode>_interna, FP16 iterator): Likewise. Diff: --- gcc/config/rs6000/rs6000.cc | 8 ++++++++ gcc/config/rs6000/rs6000.h | 2 +- gcc/config/rs6000/rs6000.md | 12 ++++++------ 3 files changed, 15 insertions(+), 7 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index a350eeca6dbe..62f208a3b379 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3952,6 +3952,14 @@ rs6000_option_override_internal (bool global_init_p) } } + /* -mbfloat16 needs -mcpu=power10. */ + if (TARGET_BFLOAT16 && !TARGET_POWER10) + { + rs6000_isa_flags &= ~OPTION_MASK_BFLOAT16; + if ((rs6000_isa_flags_explicit & OPTION_MASK_BFLOAT16) != 0) + warning (0, "%qs needs at least %qs", "-mbfloat16", "-mcpu=power10"); + } + /* If hard-float/altivec/vsx were explicitly turned off then don't allow the -mcpu setting to enable options that conflict. */ if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX) diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 98c3ae93fa08..b44287a74a6e 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -574,7 +574,7 @@ extern int rs6000_vector_align[]; #define FP16_SCALAR_P(MODE) \ (((MODE) == HFmode && TARGET_IEEE16) \ - || ((MODE) == BFmode && TARGET_BFLOAT16 && TARGET_POWER10)) + || ((MODE) == BFmode && TARGET_BFLOAT16)) /* Whether the various reciprocal divide/square root estimate instructions exist, and whether we should automatically generate code for the instruction diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index c6b6d7e9ad54..c1d6a7ba79db 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -860,7 +860,8 @@ (DI "TARGET_POWERPC64")]) ;; Mode iterator for supported 16-bit floating point types. -(define_mode_iterator FP16 [HF BF]) +(define_mode_iterator FP16 [(HF "TARGET_IEEE16") + (BF "TARGET_BFLOAT16")]) ;; Mode iterator for floating point modes other than SF/DFmode that we ;; convert to/from _Float16 (HFmode) via DFmode. @@ -8204,7 +8205,7 @@ (define_expand "mov<mode>" [(set (match_operand:FP16 0 "nonimmediate_operand") (match_operand:FP16 1 "any_operand"))] - "FP16_SCALAR_P (<MODE>mode)" + "" { if (MEM_P (operands[0]) && !REG_P (operands[1])) operands[1] = force_reg (<MODE>mode, operands[1]); @@ -8215,7 +8216,7 @@ (define_insn "*mov<mode>_xxspltiw" [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,r") (match_operand:FP16 1 "fp16_xxspltiw_constant" "eP,eP"))] - "FP16_SCALAR_P (<MODE>mode) && TARGET_POWER10 && TARGET_PREFIXED" + "TARGET_POWER10 && TARGET_PREFIXED" { rtx op1 = operands[1]; const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op1); @@ -8238,9 +8239,8 @@ (match_operand:FP16 1 "any_operand" "wa, Z, wa, r, m, r, wa, r, j, j"))] - "FP16_SCALAR_P (<MODE>mode) - && (gpc_reg_operand (operands[0], <MODE>mode) - || gpc_reg_operand (operands[1], <MODE>mode))" + "(gpc_reg_operand (operands[0], <MODE>mode) + || gpc_reg_operand (operands[1], <MODE>mode))" "@ xxlor %x0,%x1,%x1 lxsihzx %x0,%y1
