https://gcc.gnu.org/g:7b0c41ca37fe3cc2fa0caeb2ff4d1754104fcaa3
commit 7b0c41ca37fe3cc2fa0caeb2ff4d1754104fcaa3 Author: Michael Meissner <[email protected]> Date: Fri Oct 17 03:49:39 2025 -0400 Fix 16-bit floating point ordering. 2025-10-17 Michael Meissner <[email protected]> gcc/ * config/rs6000/ffloat16.md (vec_unpacks_hi_v8hf): Fix ordering issue. (vec_unpacks_lo_v8hf): Likewise. (vec_unpacks_hi_v8bf): Likewise. (vec_unpacks_lo_v8bf): Likewise. Diff: --- gcc/config/rs6000/float16.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md index 1ea070c4486e..c868dbc1ad93 100644 --- a/gcc/config/rs6000/float16.md +++ b/gcc/config/rs6000/float16.md @@ -1013,7 +1013,7 @@ { rtx reg = gen_reg_rtx (V8HFmode); - rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); + rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); emit_insn (gen_xvcvhpsp_v8hf (operands[0], reg)); DONE; }) @@ -1025,7 +1025,7 @@ { rtx reg = gen_reg_rtx (V8HFmode); - rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); + rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); emit_insn (gen_xvcvhpsp_v8hf (operands[0], reg)); DONE; }) @@ -1047,7 +1047,7 @@ { rtx reg = gen_reg_rtx (V8BFmode); - rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); + rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); emit_insn (gen_xvcvbf16spn_v8bf (operands[0], reg)); DONE; }) @@ -1059,7 +1059,7 @@ { rtx reg = gen_reg_rtx (V8BFmode); - rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); + rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); emit_insn (gen_xvcvbf16spn_v8bf (operands[0], reg)); DONE; })
