https://gcc.gnu.org/g:b05011dca9e0833debb996259fce6b99b6455d35
commit b05011dca9e0833debb996259fce6b99b6455d35 Author: Michael Meissner <[email protected]> Date: Tue Oct 21 22:12:59 2025 -0400 Move stuff from vsx.md to float16.md. 2025-10-21 Michael Meissner <[email protected]> gcc/ * config/rs6000/float16.md (extendbf<mode>2): Rename vsx_xscvspdpn_sf to xscvspdpn_sf and move it from vsx.md to float16.md. Rename vsx_xscvdpspn_sf to xscvdpspn_sf. (xscvdpspn_sf): Likewise. (xscvspdpn_sf): Likewise. (trunc<mode>bf2): Likewise. * config/rs6000/vsx.md (vsx_xscvspdpn_sf): Likewise. Diff: --- gcc/config/rs6000/float16.md | 26 +++++++++++++++++++------- gcc/config/rs6000/vsx.md | 8 -------- 2 files changed, 19 insertions(+), 15 deletions(-) diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md index 677910268a38..fb8182c65052 100644 --- a/gcc/config/rs6000/float16.md +++ b/gcc/config/rs6000/float16.md @@ -227,7 +227,7 @@ /* XSCVSPNDP -- convert single V4SFmode element to DFmode. */ emit_insn (GET_MODE (op0) == SFmode - ? gen_vsx_xscvspdpn_sf (op0, op2_v4sf) + ? gen_xscvspdpn_sf (op0, op2_v4sf) : gen_vsx_xscvspdpn (op0, op2_v4sf)); DONE; @@ -235,12 +235,24 @@ [(set_attr "type" "fpsimple") (set_attr "length" "12")]) -(define_insn "vsx_xscvdpsp_sf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=f,?wa") - (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "f,wa")] +;; Convert a SFmode scalar represented as DFmode to elements 0 and 1 of +;; V4SFmode. +(define_insn "xscvdpspn_sf" + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") + (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "wa")] UNSPEC_VSX_CVSPDP))] - "VECTOR_UNIT_VSX_P (DFmode)" - "xscvdpsp %x0,%x1" + "VECTOR_UNIT_VSX_P (SFmode)" + "xscvdpspn %x0,%x1" + [(set_attr "type" "fp")]) + +;; Convert element 0 of a V4SFmode to scalar SFmode (which on the +;; PowerPC uses the DFmode encoding). +(define_insn "xscvspdpn_sf" + [(set (match_operand:SF 0 "vsx_register_operand" "=wa") + (unspec:SF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] + UNSPEC_VSX_CVSPDPN))] + "TARGET_XSCVSPDPN" + "xscvspdpn %x0,%x1" [(set_attr "type" "fp")]) ;; Vector shift left by 32 bits to get the 16-bit floating point value @@ -277,7 +289,7 @@ op2 = gen_reg_rtx (V4SFmode); emit_insn (GET_MODE (op1) == SFmode - ? gen_vsx_xscvdpspn_sf (op2, op1) + ? gen_xscvdpspn_sf (op2, op1) : gen_vsx_xscvdpspn (op2, op1)); emit_insn (gen_xvcvspbf16_bf (op0, op2)); diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 6c11d7766ed1..3198802dabb9 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -2489,14 +2489,6 @@ "xscvspdpn %x0,%x1" [(set_attr "type" "fp")]) -(define_insn "vsx_xscvspdpn_sf" - [(set (match_operand:SF 0 "vsx_register_operand" "=wa") - (unspec:SF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVSPDPN))] - "TARGET_XSCVSPDPN" - "xscvspdpn %x0,%x1" - [(set_attr "type" "fp")]) - (define_insn "vsx_xscvdpspn_scalar" [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "wa")]
