https://gcc.gnu.org/g:446be97b4a336d04ed280c12dfe111eb94fd9432
commit 446be97b4a336d04ed280c12dfe111eb94fd9432 Author: Michael Meissner <[email protected]> Date: Thu Oct 23 19:40:35 2025 -0400 Remove V8BFmode and V8HFmode vector unary operations. 2025-10-23 Michael Meissner <[email protected]> gcc/ * config/rs6000/float16.cc (bfloat16_operation_as_v4sf): Remove vector unary operations. (fp16_vectorization): Likewise. (neg<mode>2): Likewise. * config/rs6000/float16.md (abs<mode>2, VFP16 iterator): Likewise. (neg_<fp16_names><mode>3, VFP16 iterator): Likewise. (abs_<fp16_names><mode>3): Likewise. (enum fp16_operation): Likewise. Diff: --- gcc/config/rs6000/float16.cc | 27 ----------- gcc/config/rs6000/float16.md | 97 --------------------------------------- gcc/config/rs6000/rs6000-protos.h | 2 - 3 files changed, 126 deletions(-) diff --git a/gcc/config/rs6000/float16.cc b/gcc/config/rs6000/float16.cc index 80f580388e57..3fb61e9e4621 100644 --- a/gcc/config/rs6000/float16.cc +++ b/gcc/config/rs6000/float16.cc @@ -88,8 +88,6 @@ bfloat16_operation_as_v4sf (enum rtx_code icode, n_opts = 3; break; - case FP16_ABS_BINARY: - case FP16_NEG_BINARY: default: gcc_unreachable (); } @@ -176,8 +174,6 @@ bfloat16_operation_as_v4sf (enum rtx_code icode, } break; - case FP16_ABS_BINARY: - case FP16_NEG_BINARY: default: gcc_unreachable (); } @@ -216,7 +212,6 @@ fp16_vectorization (enum rtx_code icode, { gcc_assert (can_create_pseudo_p ()); - enum rtx_code unary_op = UNKNOWN; machine_mode result_mode = GET_MODE (result); rtx op_orig[3] = { op1, op2, op3 }; rtx op_hi[3]; @@ -231,16 +226,6 @@ fp16_vectorization (enum rtx_code icode, n_opts = 2; break; - case FP16_NEG_BINARY: - n_opts = 2; - unary_op = NEG; - break; - - case FP16_ABS_BINARY: - n_opts = 2; - unary_op = ABS; - break; - case FP16_FMA: case FP16_FMS: case FP16_NFMA: @@ -289,8 +274,6 @@ fp16_vectorization (enum rtx_code icode, switch (subtype) { case FP16_BINARY: - case FP16_NEG_BINARY: - case FP16_ABS_BINARY: emit_insn (gen_rtx_SET (result_hi, gen_rtx_fmt_ee (icode, V4SFmode, op_hi[0], @@ -339,16 +322,6 @@ fp16_vectorization (enum rtx_code icode, gcc_unreachable (); } - /* Add any unary operator modifications. */ - if (unary_op != UNKNOWN) - { - emit_insn (gen_rtx_SET (result_hi, - gen_rtx_fmt_e (unary_op, V4SFmode, result_hi))); - - emit_insn (gen_rtx_SET (result_lo, - gen_rtx_fmt_e (unary_op, V4SFmode, result_lo))); - } - /* Combine the 2 V4SFmode operations into one V8HFmode/V8BFmode vector. */ if (result_mode == V8HFmode) emit_insn (gen_vec_pack_trunc_v4sf_v8hf (result, result_hi, result_lo)); diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md index a8c2747f7de3..f2ca23e8224d 100644 --- a/gcc/config/rs6000/float16.md +++ b/gcc/config/rs6000/float16.md @@ -775,69 +775,6 @@ ;; Add vectorization support for 16-bit floating point. -;; Negate vector bfloat16/float16 -(define_insn_and_split "neg<mode>2" - [(set (match_operand:VFP16 0 "vsx_register_operand" "=wa") - (neg:VFP16 - (match_operand:VFP16 1 "vsx_register_operand" "wa"))) - (clobber (match_scratch:VFP16 2 "=&wa"))] - "" - "#" - "&& 1" - [(set (match_dup 2) - (vec_duplicate:VFP16 (match_dup 3))) - (set (match_dup 0) - (xor:VFP16 (match_dup 1) - (match_dup 2)))] -{ - if (GET_CODE (operands[2]) == SCRATCH) - operands[2] = gen_reg_rtx (<MODE>mode); - - REAL_VALUE_TYPE dconst; - - gcc_assert (real_from_string (&dconst, "-0.0") == 0); - - rtx neg0 = const_double_from_real_value (dconst, <VEC_base>mode); - if (!TARGET_POWER10 || !TARGET_PREFIXED) - neg0 = force_reg (<VEC_base>mode, neg0); - - operands[3] = neg0; -} - [(set_attr "type" "veclogical") - (set_attr "length" "16")]) - -;; 16-bit floating point vector absolute value - -(define_insn_and_split "abs<mode>2" - [(set (match_operand:VFP16 0 "vsx_register_operand" "=wa") - (abs:VFP16 - (match_operand:VFP16 1 "vsx_register_operand" "wa"))) - (clobber (match_scratch:VFP16 2 "=&wa"))] - "" - "#" - "&& 1" - [(set (match_dup 2) - (vec_duplicate:VFP16 (match_dup 3))) - (set (match_dup 0) - (and:VFP16 (match_dup 1) - (not:VFP16 (match_dup 2))))] -{ - if (GET_CODE (operands[2]) == SCRATCH) - operands[2] = gen_reg_rtx (<MODE>mode); - - REAL_VALUE_TYPE dconst; - - gcc_assert (real_from_string (&dconst, "-0.0") == 0); - - rtx neg0 = const_double_from_real_value (dconst, <VEC_base>mode); - if (!TARGET_POWER10 || !TARGET_PREFIXED) - neg0 = force_reg (<VEC_base>mode, neg0); - - operands[3] = neg0; -} - [(set_attr "type" "veclogical") - (set_attr "length" "16")]) - ;; Binary operators being vectorized. (define_insn_and_split "<fp16_names><mode>3" [(set (match_operand:VFP16_HW 0 "vsx_register_operand") @@ -854,40 +791,6 @@ DONE; }) -;; Negative of binary operators being vectorized. -(define_insn_and_split "*neg_<fp16_names><mode>3" - [(set (match_operand:VFP16_HW 0 "vsx_register_operand") - (neg:VFP16_HW - (FP16_BINARY_OP:VFP16_HW - (match_operand:VFP16_HW 1 "vsx_register_operand") - (match_operand:VFP16_HW 2 "vsx_register_operand"))))] - "can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - fp16_vectorization (<CODE>, operands[0], operands[1], operands[2], - NULL_RTX, FP16_NEG_BINARY); - DONE; -}) - -;; Absolute value of binary operators being vectorized. -(define_insn_and_split "*abs_<fp16_names><mode>3" - [(set (match_operand:VFP16_HW 0 "vsx_register_operand") - (abs:VFP16_HW - (FP16_BINARY_OP:VFP16_HW - (match_operand:VFP16_HW 1 "vsx_register_operand") - (match_operand:VFP16_HW 2 "vsx_register_operand"))))] - "can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - fp16_vectorization (<CODE>, operands[0], operands[1], operands[2], - NULL_RTX, FP16_ABS_BINARY); - DONE; -}) - ;; FMA operations being vectorized. (define_insn_and_split "fma<mode>4" [(set (match_operand:VFP16_HW 0 "vsx_register_operand") diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index ee96e0e50a0e..3c4d21299e1a 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -263,8 +263,6 @@ extern unsigned constant_generates_xxspltidp (vec_const_128bit_type *); /* Optimize bfloat16 and float16 operations. */ enum fp16_operation { FP16_BINARY, /* Bfloat16/float16 binary op. */ - FP16_ABS_BINARY, /* abs (binary op). */ - FP16_NEG_BINARY, /* - (binary op). */ FP16_FMA, /* (a * b) + c. */ FP16_FMS, /* (a * b) - c. */ FP16_NFMA, /* - ((a * b) + c). */
