https://gcc.gnu.org/g:0be6ce25775c51bf30cb2b411b8cbe3a109e49ad
commit 0be6ce25775c51bf30cb2b411b8cbe3a109e49ad Author: Michael Meissner <[email protected]> Date: Thu Oct 23 21:09:29 2025 -0400 Move BFmode and HFmode logical operations to float16.md. 2025-10-23 Michael Meissner <[email protected]> gcc/ * config/rs6000/float16.md (and<mode>3): Move BFmode/HFmode logical operations here from rs6000.md. (ior<mode>): Likewise. (xor<mode>3): Likewise. (nor<mode>3): Likewise. (andn<mode>3): Likewise. (eqv<mode>3): Likewise. (nand<mode>3): Likewise. (iorn<mode>3): Likewise. (bool<mode>3): Likewise. (boolc<mode>3): Likewise. (boolcc<mode>): Likewise. * config/rs6000/rs6000.md (BOOL_128): Likewise. (BOOL_REGS_OUTPUT): Likewise. (BOOL_REGS_OP1): Likewise. (BOOL_REGS_OP2): Likewise. (BOOL_REGS_UNARY): Likewise. Diff: --- gcc/config/rs6000/float16.md | 100 +++++++++++++++++++++++++++++++++++++++++++ gcc/config/rs6000/rs6000.md | 10 ----- 2 files changed, 100 insertions(+), 10 deletions(-) diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md index f2ca23e8224d..cc7a00c6a0d1 100644 --- a/gcc/config/rs6000/float16.md +++ b/gcc/config/rs6000/float16.md @@ -174,6 +174,106 @@ [(set_attr "type" "veclogical,vecperm") (set_attr "prefixed" "*,yes")]) +;; Add logical operations for 16-bit floating point types that are +;; used for things like negate, abs, and extracting exponents. +(define_expand "and<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand") + (and:FP16 (match_operand:FP16 1 "gpc_reg_operand") + (match_operand:FP16 2 "gpc_reg_operand")))] + "" + "") + +(define_expand "ior<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand") + (ior:FP16 (match_operand:FP16 1 "gpc_reg_operand") + (match_operand:FP16 2 "gpc_reg_operand")))] + "" + "") + +(define_expand "xor<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand") + (xor:FP16 (match_operand:FP16 1 "gpc_reg_operand") + (match_operand:FP16 2 "gpc_reg_operand")))] + "" + "") + +(define_expand "nor<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand") + (and:FP16 + (not:FP16 (match_operand:FP16 1 "gpc_reg_operand")) + (not:FP16 (match_operand:FP16 2 "gpc_reg_operand"))))] + "" + "") + +(define_expand "andn<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand") + (and:FP16 + (not:FP16 (match_operand:FP16 2 "gpc_reg_operand")) + (match_operand:FP16 1 "gpc_reg_operand")))] + "" + "") + +(define_expand "eqv<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand") + (not:FP16 + (xor:FP16 (match_operand:FP16 1 "gpc_reg_operand") + (match_operand:FP16 2 "gpc_reg_operand"))))] + "" + "") + +;; Rewrite nand into canonical form +(define_expand "nand<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand") + (ior:FP16 + (not:FP16 (match_operand:FP16 1 "gpc_reg_operand")) + (not:FP16 (match_operand:FP16 2 "gpc_reg_operand"))))] + "" + "") + +;; The canonical form is to have the negated element first, so we need to +;; reverse arguments. +(define_expand "iorn<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand") + (ior:FP16 + (not:FP16 (match_operand:FP16 2 "gpc_reg_operand")) + (match_operand:FP16 1 "gpc_reg_operand")))] + "" + "") + +(define_insn "*bool<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,r") + (match_operator:FP16 3 "boolean_operator" + [(match_operand:FP16 1 "gpc_reg_operand" "wa,r") + (match_operand:FP16 2 "gpc_reg_operand" "wa,r")]))] + "" + "@ + xxl%q3 %x0,%x1,%x2 + %q3 %0,%1,%2" + [(set_attr "type" "veclogical,logical")]) + +(define_insn "*boolc<mode>3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=wa,r") + (match_operator:GPR 3 "boolean_operator" + [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "wa,r")) + (match_operand:GPR 1 "gpc_reg_operand" "wa,r")]))] + "" + "@ + xxl%q3 %x0,%x1,%x0 + %q3 %0,%1,%2" + [(set_attr "type" "veclogical,logical")]) + +(define_insn "*boolcc<mode>3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=wa,r") + (match_operator:GPR 3 "boolean_operator" + [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "wa,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "wa,r"))]))] + "" + "@ + xxl%q3 %x0,%x1,%x2 + %q3 %0,%1,%2" + [(set_attr "type" "veclogical,logical")]) + + ;; Convert IEEE 16-bit floating point to/from other floating point modes. (define_insn "extendhf<mode>2" diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9d6549bae6be..cc78e6e6e5d2 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -786,9 +786,7 @@ (V16QI "TARGET_ALTIVEC") (V8HI "TARGET_ALTIVEC") (V8BF "TARGET_BFLOAT16") - (BF "TARGET_BFLOAT16") (V8HF "TARGET_FLOAT16") - (HF "TARGET_FLOAT16") (V4SI "TARGET_ALTIVEC") (V4SF "TARGET_ALTIVEC") (V2DI "TARGET_ALTIVEC") @@ -807,9 +805,7 @@ (V16QI "wa,v,&?r,?r,?r") (V8HI "wa,v,&?r,?r,?r") (V8BF "wa,v,&?r,?r,?r") - (BF "wa,v,&?r,?r,?r") (V8HF "wa,v,&?r,?r,?r") - (HF "wa,v,&?r,?r,?r") (V4SI "wa,v,&?r,?r,?r") (V4SF "wa,v,&?r,?r,?r") (V2DI "wa,v,&?r,?r,?r") @@ -822,9 +818,7 @@ (V16QI "wa,v,r,0,r") (V8HI "wa,v,r,0,r") (V8BF "wa,v,r,0,r") - (BF "wa,v,r,0,r") (V8HF "wa,v,r,0,r") - (HF "wa,v,r,0,r") (V4SI "wa,v,r,0,r") (V4SF "wa,v,r,0,r") (V2DI "wa,v,r,0,r") @@ -837,9 +831,7 @@ (V16QI "wa,v,r,r,0") (V8HI "wa,v,r,r,0") (V8BF "wa,v,r,r,0") - (BF "wa,v,r,r,0") (V8HF "wa,v,r,r,0") - (HF "wa,v,r,r,0") (V4SI "wa,v,r,r,0") (V4SF "wa,v,r,r,0") (V2DI "wa,v,r,r,0") @@ -854,9 +846,7 @@ (V16QI "wa,v,r,0,0") (V8HI "wa,v,r,0,0") (V8BF "wa,v,r,0,0") - (BF "wa,v,r,0,0") (V8HF "wa,v,r,0,0") - (HF "wa,v,r,0,0") (V4SI "wa,v,r,0,0") (V4SF "wa,v,r,0,0") (V2DI "wa,v,r,0,0")
