https://gcc.gnu.org/g:96353db378b9d6bbb58903a353840c79b2982d82
commit 96353db378b9d6bbb58903a353840c79b2982d82 Author: Michael Meissner <[email protected]> Date: Mon Oct 27 17:56:17 2025 -0400 Revert changes Diff: --- gcc/ChangeLog.test | 280 +---------------------- gcc/config/rs6000/float16.md | 451 ------------------------------------- gcc/config/rs6000/rs6000.cc | 9 +- gcc/config/rs6000/rs6000.h | 10 - gcc/config/rs6000/rs6000.md | 10 + libgcc/config.host | 12 - libgcc/config/rs6000/sfp-machine.h | 50 ---- libgcc/config/rs6000/t-bfloat16 | 30 --- libgcc/config/rs6000/t-both-fp16 | 28 --- libgcc/config/rs6000/t-float16 | 31 --- libgcc/configure | 44 ---- libgcc/configure.ac | 20 -- 12 files changed, 19 insertions(+), 956 deletions(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test index fae3ec5528a5..c12fc70339b6 100644 --- a/gcc/ChangeLog.test +++ b/gcc/ChangeLog.test @@ -1,277 +1,9 @@ -==================== Branch work223-test, patch #415 ==================== - -Move BFmode and HFmode logical operations to float16.md. - -2025-10-23 Michael Meissner <[email protected]> - -gcc/ - - * config/rs6000/float16.md (and<mode>3): Move BFmode/HFmode logical - operations here from rs6000.md. - (ior<mode>): Likewise. - (xor<mode>3): Likewise. - (nor<mode>3): Likewise. - (andn<mode>3): Likewise. - (eqv<mode>3): Likewise. - (nand<mode>3): Likewise. - (iorn<mode>3): Likewise. - (bool<mode>3): Likewise. - (boolc<mode>3): Likewise. - (boolcc<mode>): Likewise. - * config/rs6000/rs6000.md (BOOL_128): Likewise. - (BOOL_REGS_OUTPUT): Likewise. - (BOOL_REGS_OP1): Likewise. - (BOOL_REGS_OP2): Likewise. - (BOOL_REGS_UNARY): Likewise. - * config/rs6000/rs6000.cc (easy_altivec_constant): Do not allow non-zero - 16-bit floating point constants. - -==================== Branch work223-test, patch #414 ==================== - -Add conversions between 16-bit floating point and other scalar modes. - -2025-10-23 Michael Meissner <[email protected]> - -gcc/ - - * config/rs6000/float16.md (fp16_float_convert): New mode iterator. - (extend<FP16_HW:mode><fp16_float_convert:mode>2): New insns to convert - between the 2 16-bit floating point modes and other floating point - scalars other than SFmode/DFmode by converting first to DFmode. - (trunc<fp16_float_convert:mode><FP16_HW:mode>2): Likewise. - (float<GPR:mode><FP16_HW:mode>2): New insns to convert beween the 2 - 16-bit floating point modes and signed/unsigned integers. - (floatuns<GPR:mode><FP16_HW:mode>2): Likewise. - (fix_trunc<FP16_HW:mode><GPR:mode>): Likewise. - (fixuns_trunc<FP16_HW:mode><GPR:mode>2): Likewise. - -==================== Branch work223-test, patch #413 ==================== - -Add conversions between __bfloat16 and float/double. - -2025-10-23 Michael Meissner <[email protected]> - -gcc/ - - * config/rs6000/float16.md (FP16_HW): Add BFmode. - (VFP16_HW): New mode iterator. - (cvt_fp16_to_v4sf_insn): New mode attribute. - (FP16_VECTOR4): Likewise. - (UNSPEC_FP16_SHIFT_LEFT_32BIT): New unspec constant. - (UNSPEC_CVT_FP16_TO_V4SF): Likewise. - (UNSPEC_XXSPLTW_FP16): Likewise. - (UNSPEC_XVCVSPBF16_BF): Likewise. - (extendbf<mode>2): New insns to convert between BFmode and - SFmode/DFmode. - (xscvdpspn_sf): Likewise. - (xscvspdpn_sf): Likewise. - (<fp16_vector8>_shift_left_32bit): Likewise. - (trunc<mode>bf): Likewise. - (vsx_xscvdpspn_sf): Likewise. - (cvt_fp16_to_v4sf_<mode): Likewise. - (cvt_fp16_to_v4sf_<mode>_le): Likewise. - (cvt_fp16_to_v4sf_<mode>_be): Likewise. - (dup_<mode>_to_v4s): Likewise. - (xxspltw_<mode>): Likewise. - (xvcvbf16spn_bf): Likewise. - (xvcvspbf16_bf): Likewise. - * config/rs6000/rs6000.h (TARGET_BFLOAT16_HW): New macro. - (FP16_HW_SCALAR_MODE_P): Add BFmode on power10. - -==================== Branch work223-test, patch #412 ==================== - -Add conversions between _Float16 and float/double. - -2025-10-23 Michael Meissner <[email protected]> - -gcc/ - - * config/rs6000/float16.md (FP16_HW): New mode iterator. - (extendhf<mode>2): Add support converting between HFmode and - SFmode/DFmoded if we are on power9 or later. - (trunc<mode>hf2): Likewise. - * config/rs6000/rs6000.h (TARGET_FLOAT16_HW): New macro. - (FP16_HW_SCALAR_MODE_P): Likewise. - -==================== Branch work223-test, patch #411 ==================== - -Add HF/BF emulation functions to libgcc. - -2025-10-23 Michael Meissner <[email protected]> - -libgcc/ - - * config.host (powerpc*-*-linux*): Add HF/BF emulation functions to - PowerPC libgcc. - * config/rs6000/sfp-machine.h (_FP_NANFRAC_H): New macro. - (_FP_NANFRAC_B): Likewise. - (_FP_NANSIGN_H): Likewise. - (_FP_NANSIGN_B): Likewise. - (DFtype2): Add HF/BF emulation function declarations. - (SFtype2): Likewise. - (DItype2): Likewise. - (UDItype2): Likewise. - (SItype2): Likewise. - (USItype2): Likewise. - (HFtype2): Likewise. - (__eqhf2): Likewise. - (__extendhfdf2): Likewise. - (__extendhfsf2): Likewise. - (__fixhfdi): Likewise. - (__fixhfsi): Likewise. - (__fixunshfdi): Likewise. - (__fixunshfsi): Likewise. - (__floatdihf): Likewise. - (__floatsihf): Likewise. - (__floatundihf): Likewise. - (__floatunsihf): Likewise. - (__truncdfhf2): Likewise. - (__truncsfhf2): Likewise. - (BFtype2): Likewise. - (__extendbfsf2): Likewise. - (__floatdibf): Likewise. - (__floatsibf): Likewise. - (__floatundibf): Likewise. - (__floatunsibf): Likewise. - (__truncdfbf2): Likewise. - (__truncsfbf2): Likewise. - (__truncbfhf2): Likewise. - (__trunchfbf2): Likewise. - * config/rs6000/t-bfloat16: New file. - * config/rs6000/t-both-fp16: Likewise. - * config/rs6000/t-float16: Likewise. - * configure.ac (powerpc*-*-linux*): Check if the PowerPC compiler - supports _Float16 and __bfloat16 types. - * configure: Regenerate. - -==================== Branch work223-test, patch #410 ==================== - -Add initial _Float16 and __bfloat16 support. - -2025-10-23 Michael Meissner <[email protected]> - -gcc/ - - * config/rs6000/altivec.md (VM): Add support for the V8HFmode and - V8BFmode vector types used for 16-bit floating point. - (VM2): Likewise. - (VI_char): Likewise. - (VI_scalar): Likewise. - (VI_char): Likewise. - (VP_small): Likewise. - (VP_small_lc): Likewise. - (VU_char): Likewise. - * config/rs6000/float16.md: New file for 16-bit floating point support. - * config/rs6000/predicates.md (fp16_xxspltiw_constant): New predicate. - * config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add support for - _Float16 and __bfloat16 types. - (rs6000_init_builtins): Define the __bfloat16 type if -mbfloat16. - * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define - __FLOAT16__ if -mfloat16. Define __BFLOAT16__ if -mbfloat16. - * config/rs6000/rs6000-call.cc (init_cumulative_args): Warn if 16-bit - floating point types are passed or returned unless -Wno-psabi is used. - (rs6000_function_arg): Likewise. - * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add a comment - for setting -mfloat16 in the future for -mcpu=power9. - (OTHER_POWER10_MASKS): Add a comment for setting -mbfloat16 for - -mcpu=power10. - (POWERPC_MASKS): Make -mfloat16 and -mbfloat16 target masks. - * config/rs6000/rs6000-modes.def (BFmode): Define modes relating to - 16-bit floating point. - (HFmode): Likewise. - (V8BFmode): Likewise. - (V8HFmode): Likewise. - (V4HFmode): Likewise. - (V4BFmode): Likewise. - * config/rs6000/rs6000-p8swap.cc (rs6000_gen_stvx): Remove #ifdef for - V8HFmode, since we now support it. Add support for V8BFmode. - (rs6000_gen_lvx): Likewise. - (replace_swapped_load_constant): Likewise. - * config/rs6000/rs6000-protos.h (vec_const_128bit_type): Add mode field - for recognizing 16-bit floating point constants. - * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add - support for the _Float16 and __bfloat16 scalr/vector types. - (rs6000_modes_tieable_p): Likewise. - (rs6000_debug_reg_global): Likewise. - (rs6000_setup_reg_addr_masks): Likewise. - (rs6000_init_hard_regno_mode_ok): Likewise. - (rs6000_option_override_internal): Add consistancy checks for -mfloat16 - and -mbfloat16. - (xxspltib_constant_p): Add support for V8HFmode and V8BFmode all 0 - vector mode constants. - (output_vec_const_move): Add 16-bit floating point scalar/vector - support. - (rs6000_expand_vector_init): Likewise. - (reg_offset_addressing_ok_p): Likewise. - (rs6000_legitimate_offset_address_p): Likewise. - (legitimate_lo_sum_address_p): Likewise. - (rs6000_const_vec): Likewise. - (rs6000_emit_move): Likewise. - (rs6000_secondary_reload_simple_move): Likewise. - (rs6000_can_change_mode_class): Likewise. - (rs6000_load_constant_and_splat): Likewise. - (rs6000_scalar_mode_supported_p): Likewise. - (rs6000_floatn_mode): Likewise. - (rs6000_opt_masks): Add -mfloat16 and -mbfloat16. - (constant_fp_to_128bit_vector): Add 16-bit floating point scalar/vector - support. - * config/rs6000/rs6000.h (FP16_SCALAR_MODE_P): New macro. - (FP16_VECTOR_MODE_P): Likewise. - (ALTIVEC_VECTOR_MODE): Add V8HFmode and V8BFmode. - * config/rs6000/rs6000.md (FMOVE128_GPR): Add V8HFmode, V8BFmode, - HFmode, and BFmode modes. - (wd): Likewise. - (du_or_d): Likewise. - (BOOL_128): Likewise. - (BOOL_REGS_OUTPUT): Likewise. - (BOOL_REGS_OP1): Likewise. - (BOOL_REGS_OP2): Likewise. - (BOOL_REGS_UNARY): Likewise. - (RELOAD): Likewise. - (toplevel): Include float16.md. - * config/rs6000/rs6000.opt (-mfloat16): New switch. - (-mbfloat16): Likewise. - * config/rs6000/vector.md (VEC_L): Add V8HFmode and V8BFmode. - (VEC_M): Likewise. - (VEC_E): Likewise. - (VEC_base): Likewise. - (VEC_base_l): Likewise. - * config/rs6000/vsx.md (VECTOR_16BIT): New mode iterator. - (VSX_L): Add V8HFmode and V8BFmode. - (VSX_M): Likewise. - (VSX_XXBR): Likewise. - (VSm): Likewise. - (VSr): Likewise. - (VSisa): Likewise. - (??r): Likewise. - (nW): Likewise. - (VSv): Likewise. - (VM3): Likewise. - (VM3_char): Likewise. - (vsx_le_perm_load_v8hi): Convert the V8HImode permute insns to also - handle V8HFmode and V8BFmode modes. - (vsx_le_perm_load_<mode>): Likewise. - (vsx_le_perm_store_v8hi): Likewise. - (vsx_le_perm_store_<mode>): Likewise. - (V8??mode splitter): Likewise. - (vsx_ld_elemrev_v8hi): Likewise. - (vsx_ld_elemrev_<mode>): Likewise. - (vsx_ld_elemrev_v8hi): Likewise. - (vsx_ld_elemrev_v8hi_internal): Likewise. - (vsx_ld_elemrev_<mode>_interna): Likewise. - (vsx_st_elemrev_v8hi): Likewise. - (vsx_st_elemrev_<mode): Likewise. - (vsx_st_elemrev_v8hi): Likewise. - (vsx_st_elemrev_<mode>_interna): Likewise. - (xxswapd_v8hi): Likewise. - (xxswapd_<mode>): Likewise. - (vsx_lxvd2x8_le_V8HI): Likewise. - (vsx_lxvd2x8_le_<MODE): Likewise. - (vsx_stxvd2x8_le_V8HI): Likewise. - (vsx_stxvd2x8_le_<MODE>): Likewise. - (vsx_extract_<mode>_store_p9): Likewise. - (vsx_extract_<mode>_p8): Likewise. - +==================== Branch work223-test, patch #415 was reverted ==================== +==================== Branch work223-test, patch #414 was reverted ==================== +==================== Branch work223-test, patch #413 was reverted ==================== +==================== Branch work223-test, patch #412 was reverted ==================== +==================== Branch work223-test, patch #411 was reverted ==================== +==================== Branch work223-test, patch #410 was reverted ==================== ==================== Branch work223-test, patch #403 was reverted ==================== ==================== Branch work223-test, patch #402 was reverted ==================== ==================== Branch work223-test, patch #401 was reverted ==================== diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md index 00c760e463c6..d186d8e7d601 100644 --- a/gcc/config/rs6000/float16.md +++ b/gcc/config/rs6000/float16.md @@ -25,26 +25,6 @@ (define_mode_iterator FP16 [(BF "TARGET_BFLOAT16") (HF "TARGET_FLOAT16")]) -;; Mode iterator for 16-bit floating point modes on machines with -;; hardware support both as a scalar and as a vector. -(define_mode_iterator FP16_HW [(BF "TARGET_BFLOAT16_HW") - (HF "TARGET_FLOAT16_HW")]) - -(define_mode_iterator VFP16_HW [(V8BF "TARGET_BFLOAT16_HW") - (V8HF "TARGET_FLOAT16_HW")]) - -;; Mode iterator for floating point modes other than SF/DFmode that we -;; convert to/from _Float16 (HFmode) via DFmode. -(define_mode_iterator fp16_float_convert [TF KF IF SD DD TD]) - -;; Mode attribute giving the instruction to convert the even -;; V8HFmode or V8BFmode elements to V4SFmode -(define_mode_attr cvt_fp16_to_v4sf_insn [(BF "xvcvbf16spn") - (HF "xvcvhpsp") - (V8BF "xvcvbf16spn") - (V8HF "xvcvhpsp")]) - -;; Mode attribute giving the vector mode for a 16-bit floating point ;; Mode attribute giving the vector mode for a 16-bit floating point ;; scalar in both upper and lower case. (define_mode_attr FP16_VECTOR8 [(BF "V8BF") @@ -52,20 +32,6 @@ (define_mode_attr fp16_vector8 [(BF "v8bf") (HF "v8hf")]) - -;; Mode attribute giving the vector mode with 4 16-bit floating point -;; elements given a scalar or 8 element vector. -(define_mode_attr FP16_VECTOR4 [(BF "V4BF") - (HF "V4HF") - (V8BF "V4BF") - (V8HF "V4HF")]) - -;; UNSPEC constants -(define_c_enum "unspec" - [UNSPEC_FP16_SHIFT_LEFT_32BIT - UNSPEC_CVT_FP16_TO_V4SF - UNSPEC_XXSPLTW_FP16 - UNSPEC_XVCVSPBF16_BF]) ;; _Float16 and __bfloat16 moves (define_expand "mov<mode>" @@ -156,420 +122,3 @@ } [(set_attr "type" "veclogical,vecperm") (set_attr "prefixed" "*,yes")]) - -;; Add logical operations for 16-bit floating point types that are -;; used for things like negate, abs, and extracting exponents. -(define_expand "and<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (and:FP16 (match_operand:FP16 1 "gpc_reg_operand") - (match_operand:FP16 2 "gpc_reg_operand")))] - "" - "") - -(define_expand "ior<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (ior:FP16 (match_operand:FP16 1 "gpc_reg_operand") - (match_operand:FP16 2 "gpc_reg_operand")))] - "" - "") - -(define_expand "xor<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (xor:FP16 (match_operand:FP16 1 "gpc_reg_operand") - (match_operand:FP16 2 "gpc_reg_operand")))] - "" - "") - -(define_expand "nor<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (and:FP16 - (not:FP16 (match_operand:FP16 1 "gpc_reg_operand")) - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand"))))] - "" - "") - -(define_expand "andn<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (and:FP16 - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand")) - (match_operand:FP16 1 "gpc_reg_operand")))] - "" - "") - -(define_expand "eqv<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (not:FP16 - (xor:FP16 (match_operand:FP16 1 "gpc_reg_operand") - (match_operand:FP16 2 "gpc_reg_operand"))))] - "" - "") - -;; Rewrite nand into canonical form -(define_expand "nand<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (ior:FP16 - (not:FP16 (match_operand:FP16 1 "gpc_reg_operand")) - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand"))))] - "" - "") - -;; The canonical form is to have the negated element first, so we need to -;; reverse arguments. -(define_expand "iorn<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (ior:FP16 - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand")) - (match_operand:FP16 1 "gpc_reg_operand")))] - "" - "") - -(define_insn "*bool<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,r") - (match_operator:FP16 3 "boolean_operator" - [(match_operand:FP16 1 "gpc_reg_operand" "wa,r") - (match_operand:FP16 2 "gpc_reg_operand" "wa,r")]))] - "" - "@ - xxl%q3 %x0,%x1,%x2 - %q3 %0,%1,%2" - [(set_attr "type" "veclogical,logical")]) - -(define_insn "*boolc<mode>3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=wa,r") - (match_operator:GPR 3 "boolean_operator" - [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "wa,r")) - (match_operand:GPR 1 "gpc_reg_operand" "wa,r")]))] - "" - "@ - xxl%q3 %x0,%x1,%x0 - %q3 %0,%1,%2" - [(set_attr "type" "veclogical,logical")]) - -(define_insn "*boolcc<mode>3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=wa,r") - (match_operator:GPR 3 "boolean_operator" - [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "wa,r")) - (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "wa,r"))]))] - "" - "@ - xxl%q3 %x0,%x1,%x2 - %q3 %0,%1,%2" - [(set_attr "type" "veclogical,logical")]) - - -;; Convert IEEE 16-bit floating point to/from other floating point modes. - -(define_insn "extendhf<mode>2" - [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa") - (float_extend:SFDF - (match_operand:HF 1 "vsx_register_operand" "wa")))] - "TARGET_FLOAT16_HW" - "xscvhpdp %x0,%x1" - [(set_attr "type" "fpsimple")]) - -(define_insn "trunc<mode>hf2" - [(set (match_operand:HF 0 "vsx_register_operand" "=wa") - (float_truncate:HF - (match_operand:SFDF 1 "vsx_register_operand" "wa")))] - "TARGET_FLOAT16_HW" - "xscvdphp %x0,%x1" - [(set_attr "type" "fpsimple")]) - -;; Convert BFmode to SFmode/DFmode. -;; 3 instructions are generated: -;; VSPLTH -- duplicate BFmode into all elements -;; XVCVBF16SPN -- convert even BFmode elements to SFmode -;; XSCVSPNDP -- convert memory format of SFmode to DFmode. -(define_insn_and_split "extendbf<mode>2" - [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa") - (float_extend:SFDF - (match_operand:BF 1 "vsx_register_operand" "v"))) - (clobber (match_scratch:V8BF 2 "=v"))] - "TARGET_BFLOAT16_HW" - "#" - "&& 1" - [(pc)] -{ - rtx op0 = operands[0]; - rtx op1 = operands[1]; - rtx op2_v8bf = operands[2]; - - if (GET_CODE (op2_v8bf) == SCRATCH) - op2_v8bf = gen_reg_rtx (V8BFmode); - - rtx op2_v4sf = gen_lowpart (V4SFmode, op2_v8bf); - - /* XXSLDWI -- shift BFmode element into the upper 32 bits. */ - emit_insn (gen_v8bf_shift_left_32bit (op2_v8bf, op1)); - - /* XVCVBF16SPN -- convert even V8BFmode elements to V4SFmode. */ - emit_insn (gen_cvt_fp16_to_v4sf_v8bf (op2_v4sf, op2_v8bf)); - - /* XSCVSPNDP -- convert single V4SFmode element to DFmode. */ - emit_insn (GET_MODE (op0) == SFmode - ? gen_xscvspdpn_sf (op0, op2_v4sf) - : gen_vsx_xscvspdpn (op0, op2_v4sf)); - - DONE; -} - [(set_attr "type" "fpsimple") - (set_attr "length" "12")]) - -;; Convert a SFmode scalar represented as DFmode to elements 0 and 1 of -;; V4SFmode. -(define_insn "xscvdpspn_sf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVSPDP))] - "VECTOR_UNIT_VSX_P (SFmode)" - "xscvdpspn %x0,%x1" - [(set_attr "type" "fp")]) - -;; Convert element 0 of a V4SFmode to scalar SFmode (which on the -;; PowerPC uses the DFmode encoding). -(define_insn "xscvspdpn_sf" - [(set (match_operand:SF 0 "vsx_register_operand" "=wa") - (unspec:SF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVSPDPN))] - "TARGET_XSCVSPDPN" - "xscvspdpn %x0,%x1" - [(set_attr "type" "fp")]) - -;; Vector shift left by 32 bits to get the 16-bit floating point value -;; into the upper 32 bits for the conversion. -(define_insn "<fp16_vector8>_shift_left_32bit" - [(set (match_operand:<FP16_VECTOR8> 0 "vsx_register_operand" "=wa") - (unspec:<FP16_VECTOR8> - [(match_operand:FP16_HW 1 "vsx_register_operand" "wa")] - UNSPEC_FP16_SHIFT_LEFT_32BIT))] - "" - "xxsldwi %x0,%x1,%x1,1" - [(set_attr "type" "vecperm")]) - -;; Convert SFmode/DFmode to BFmode. -;; 2 instructions are generated: -;; XSCVDPSPN -- convert SFmode/DFmode scalar to V4SFmode -;; XVCVSPBF16 -- convert V4SFmode to even V8BFmode - -(define_insn_and_split "trunc<mode>bf2" - [(set (match_operand:BF 0 "vsx_register_operand" "=wa") - (float_truncate:BF - (match_operand:SFDF 1 "vsx_register_operand" "wa"))) - (clobber (match_scratch:V4SF 2 "=wa"))] - "TARGET_BFLOAT16_HW" - "#" - "&& 1" - [(pc)] -{ - rtx op0 = operands[0]; - rtx op1 = operands[1]; - rtx op2 = operands[2]; - - if (GET_CODE (op2) == SCRATCH) - op2 = gen_reg_rtx (V4SFmode); - - emit_insn (GET_MODE (op1) == SFmode - ? gen_xscvdpspn_sf (op2, op1) - : gen_vsx_xscvdpspn (op2, op1)); - - emit_insn (gen_xvcvspbf16_bf (op0, op2)); - DONE; -} - [(set_attr "type" "fpsimple")]) - -(define_insn "vsx_xscvdpspn_sf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVDPSPN))] - "TARGET_XSCVDPSPN" - "xscvdpspn %x0,%x1" - [(set_attr "type" "fp")]) - -;; Convert the even elements of a vector 16-bit floating point to -;; V4SFmode. Deal with little endian vs. big endian element ordering -;; in identifying which elements are converted. - -(define_expand "cvt_fp16_to_v4sf_<mode>" - [(set (match_operand:V4SF 0 "vsx_register_operand") - (float_extend:V4SF - (vec_select:<FP16_VECTOR4> - (match_operand:VFP16_HW 1 "vsx_register_operand") - (parallel [(match_dup 2) - (match_dup 3) - (match_dup 4) - (match_dup 5)]))))] - "" -{ - int endian_adjust = WORDS_BIG_ENDIAN ? 0 : 1; - operands[2] = GEN_INT (0 + endian_adjust); - operands[3] = GEN_INT (2 + endian_adjust); - operands[4] = GEN_INT (4 + endian_adjust); - operands[5] = GEN_INT (6 + endian_adjust); -}) - -(define_insn "*cvt_fp16_to_v4sf_<mode>_le" - [(set (match_operand:V4SF 0 "vsx_register_operand") - (float_extend:V4SF - (vec_select:<FP16_VECTOR4> - (match_operand:VFP16_HW 1 "vsx_register_operand") - (parallel [(const_int 1) - (const_int 3) - (const_int 5) - (const_int 7)]))))] - "!WORDS_BIG_ENDIAN" - "<cvt_fp16_to_v4sf_insn> %x0,%x1" - [(set_attr "type" "vecfloat")]) - -(define_insn "*cvt_fp16_to_v4sf_<mode>_be" - [(set (match_operand:V4SF 0 "vsx_register_operand") - (float_extend:V4SF - (vec_select:<FP16_VECTOR4> - (match_operand:VFP16_HW 1 "vsx_register_operand") - (parallel [(const_int 0) - (const_int 2) - (const_int 4) - (const_int 6)]))))] - "WORDS_BIG_ENDIAN" - "<cvt_fp16_to_v4sf_insn> %x0,%x1" - [(set_attr "type" "vecfloat")]) - -;; Duplicate and convert a 16-bit floating point scalar to V4SFmode. - -(define_insn_and_split "*dup_<mode>_to_v4sf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (vec_duplicate:V4SF - (float_extend:SF - (match_operand:FP16_HW 1 "vsx_register_operand" "wa"))))] - "" - "#" - "&& 1" - [(pc)] -{ - rtx op0 = operands[0]; - rtx op1 = operands[1]; - rtx op0_vfp16 = gen_lowpart (<FP16_VECTOR8>mode, op0); - - emit_insn (gen_xxspltw_<mode> (op0, op1)); - emit_insn (gen_cvt_fp16_to_v4sf_<fp16_vector8> (op0, op0_vfp16)); - DONE; -} - [(set_attr "length" "8") - (set_attr "type" "vecperm")]) - -;; Duplicate a HF/BF value so it can be used for xvcvhpspn/xvcvbf16spn. -;; Because xvcvhpspn/xvcvbf16spn only uses the even elements, we can -;; use xxspltw instead of vspltw. This has the advantage that the -;; register allocator can use any of the 64 VSX registers instead of -;; being limited to the 32 Altivec registers that VSPLTH would require. - -(define_insn "xxspltw_<mode>" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:FP16_HW 1 "vsx_register_operand" "wa")] - UNSPEC_XXSPLTW_FP16))] - "" - "xxspltw %x0,%x1,1" - [(set_attr "type" "vecperm")]) - -;; Convert a bfloat16 floating point scalar that has been splatted to -;; V4SFmode. - -(define_insn "xvcvbf16spn_bf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_CVT_FP16_TO_V4SF))] - "TARGET_BFLOAT16_HW" - "xvcvbf16spn %x0,%x1" - [(set_attr "type" "vecperm")]) - -;; Convert a V4SFmode vector to a 16-bit floating point scalar. We -;; only care about the 2nd V4SFmode element, which is the element we -;; converted the 16-bit scalar (4th element) to V4SFmode to do the -;; operation, and converted it back. - -(define_insn "xvcvspbf16_bf" - [(set (match_operand:BF 0 "vsx_register_operand" "=wa") - (unspec:BF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_XVCVSPBF16_BF))] - "TARGET_BFLOAT16_HW" - "xvcvspbf16 %x0,%x1" - [(set_attr "type" "vecfloat")]) - -;; Convert between HFmode/BFmode and 128-bit binary floating point and -;; decimal floating point types. We use convert_move since some of the -;; types might not have valid RTX expanders. We use DFmode as the -;; intermediate conversion destination. - -(define_expand "extend<FP16_HW:mode><fp16_float_convert:mode>2" - [(set (match_operand:fp16_float_convert 0 "vsx_register_operand") - (float_extend:fp16_float_convert - (match_operand:FP16_HW 1 "vsx_register_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - emit_insn (gen_extend<FP16_HW:mode>df2 (df_tmp, operands[1])); - convert_move (operands[0], df_tmp, 0); - DONE; -}) - -(define_expand "trunc<fp16_float_convert:mode><FP16_HW:mode>2" - [(set (match_operand:FP16_HW 0 "vsx_register_operand") - (float_truncate:FP16_HW - (match_operand:fp16_float_convert 1 "vsx_register_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - - convert_move (df_tmp, operands[1], 0); - emit_insn (gen_truncdf<FP16_HW:mode>2 (operands[0], df_tmp)); - DONE; -}) - -;; Convert integers to 16-bit floating point modes. -(define_expand "float<GPR:mode><FP16_HW:mode>2" - [(set (match_operand:FP16_HW 0 "vsx_register_operand") - (float:FP16_HW - (match_operand:GPR 1 "nonimmediate_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - emit_insn (gen_float<GPR:mode>df2 (df_tmp, operands[1])); - emit_insn (gen_truncdf<FP16_HW:mode>2 (operands[0], df_tmp)); - DONE; -}) - -(define_expand "floatuns<GPR:mode><FP16_HW:mode>2" - [(set (match_operand:FP16_HW 0 "vsx_register_operand") - (unsigned_float:FP16_HW - (match_operand:GPR 1 "nonimmediate_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - emit_insn (gen_floatuns<GPR:mode>df2 (df_tmp, operands[1])); - emit_insn (gen_truncdf<FP16_HW:mode>2 (operands[0], df_tmp)); - DONE; -}) - -;; Convert 16-bit floating point modes to integers -(define_expand "fix_trunc<FP16_HW:mode><GPR:mode>2" - [(set (match_operand:GPR 0 "vsx_register_operand") - (fix:GPR - (match_operand:FP16_HW 1 "vsx_register_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - emit_insn (gen_extend<FP16_HW:mode>df2 (df_tmp, operands[1])); - emit_insn (gen_fix_truncdf<GPR:mode>2 (operands[0], df_tmp)); - DONE; -}) - -(define_expand "fixuns_trunc<FP16_HW:mode><GPR:mode>2" - [(set (match_operand:GPR 0 "vsx_register_operand") - (unsigned_fix:GPR - (match_operand:FP16_HW 1 "vsx_register_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - emit_insn (gen_extend<FP16_HW:mode>df2 (df_tmp, operands[1])); - emit_insn (gen_fixuns_truncdf<GPR:mode>2 (operands[0], df_tmp)); - DONE; -}) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index f2c39aacc9a3..e57a099466dc 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -6517,12 +6517,9 @@ easy_altivec_constant (rtx op, machine_mode mode) else if (mode != GET_MODE (op)) return 0; - /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy constants. - Likewise, don't handle 16-bit floating point constants here, unless they - are 0.0. */ - if (mode == V2DFmode - || FP16_SCALAR_MODE_P (mode) - || FP16_VECTOR_MODE_P (mode)) + /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy + constants. */ + if (mode == V2DFmode) return zero_constant (op, mode) ? 8 : 0; else if (mode == V2DImode) diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 7850affe6afc..0249219bbbc9 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -343,21 +343,11 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); || ((MODE) == TDmode) \ || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))) -/* Do we have conversion support in hardware for the 16-bit floating point? */ -#define TARGET_BFLOAT16_HW (TARGET_BFLOAT16 && TARGET_POWER10) -#define TARGET_FLOAT16_HW (TARGET_FLOAT16 && TARGET_POWER9) - /* Is this a valid 16-bit scalar floating point mode? */ #define FP16_SCALAR_MODE_P(MODE) \ (((MODE) == HFmode && TARGET_FLOAT16) \ || ((MODE) == BFmode && TARGET_BFLOAT16)) -/* Is this a valid 16-bit scalar floating point mode that has hardware - conversions? */ -#define FP16_HW_SCALAR_MODE_P(MODE) \ - (((MODE) == HFmode && TARGET_FLOAT16_HW) \ - || ((MODE) == BFmode && TARGET_BFLOAT16_HW)) - /* Is this a valid 16-bit vector floating point mode? */ #define FP16_VECTOR_MODE_P(MODE) \ (((MODE) == V8HFmode && TARGET_FLOAT16) \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index cc78e6e6e5d2..9d6549bae6be 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -786,7 +786,9 @@ (V16QI "TARGET_ALTIVEC") (V8HI "TARGET_ALTIVEC") (V8BF "TARGET_BFLOAT16") + (BF "TARGET_BFLOAT16") (V8HF "TARGET_FLOAT16") + (HF "TARGET_FLOAT16") (V4SI "TARGET_ALTIVEC") (V4SF "TARGET_ALTIVEC") (V2DI "TARGET_ALTIVEC") @@ -805,7 +807,9 @@ (V16QI "wa,v,&?r,?r,?r") (V8HI "wa,v,&?r,?r,?r") (V8BF "wa,v,&?r,?r,?r") + (BF "wa,v,&?r,?r,?r") (V8HF "wa,v,&?r,?r,?r") + (HF "wa,v,&?r,?r,?r") (V4SI "wa,v,&?r,?r,?r") (V4SF "wa,v,&?r,?r,?r") (V2DI "wa,v,&?r,?r,?r") @@ -818,7 +822,9 @@ (V16QI "wa,v,r,0,r") (V8HI "wa,v,r,0,r") (V8BF "wa,v,r,0,r") + (BF "wa,v,r,0,r") (V8HF "wa,v,r,0,r") + (HF "wa,v,r,0,r") (V4SI "wa,v,r,0,r") (V4SF "wa,v,r,0,r") (V2DI "wa,v,r,0,r") @@ -831,7 +837,9 @@ (V16QI "wa,v,r,r,0") (V8HI "wa,v,r,r,0") (V8BF "wa,v,r,r,0") + (BF "wa,v,r,r,0") (V8HF "wa,v,r,r,0") + (HF "wa,v,r,r,0") (V4SI "wa,v,r,r,0") (V4SF "wa,v,r,r,0") (V2DI "wa,v,r,r,0") @@ -846,7 +854,9 @@ (V16QI "wa,v,r,0,0") (V8HI "wa,v,r,0,0") (V8BF "wa,v,r,0,0") + (BF "wa,v,r,0,0") (V8HF "wa,v,r,0,0") + (HF "wa,v,r,0,0") (V4SI "wa,v,r,0,0") (V4SF "wa,v,r,0,0") (V2DI "wa,v,r,0,0") diff --git a/libgcc/config.host b/libgcc/config.host index ea5853d34b79..82ea1772f516 100644 --- a/libgcc/config.host +++ b/libgcc/config.host @@ -1302,18 +1302,6 @@ powerpc*-*-linux*) tmake_file="${tmake_file} rs6000/t-float128-p10-hw" fi - if test $libgcc_cv_powerpc_float16 = yes; then - tmake_file="${tmake_file} rs6000/t-float16" - fi - - if test $libgcc_cv_powerpc_bfloat16 = yes; then - tmake_file="${tmake_file} rs6000/t-bfloat16" - - if test $libgcc_cv_powerpc_bfloat16 = yes; then - tmake_file="${tmake_file} rs6000/t-both-fp16" - fi - fi - extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o" md_unwind_header=rs6000/linux-unwind.h ;; diff --git a/libgcc/config/rs6000/sfp-machine.h b/libgcc/config/rs6000/sfp-machine.h index 642d2fc4f215..f0ede0e042a3 100644 --- a/libgcc/config/rs6000/sfp-machine.h +++ b/libgcc/config/rs6000/sfp-machine.h @@ -22,9 +22,6 @@ typedef unsigned int UTItype __attribute__ ((mode (TI))); #define _FP_I_TYPE int #endif /* 32-bits */ -#define _FP_NANFRAC_H _FP_QNANBIT_H -#define _FP_NANFRAC_B _FP_QNANBIT_B - /* The type of the result of a floating point comparison. This must match `__libgcc_cmp_return__' in GCC for the target. */ typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__))); @@ -65,8 +62,6 @@ typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__))); #define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1 #endif -#define _FP_NANSIGN_H 1 -#define _FP_NANSIGN_B 1 #define _FP_NANSIGN_S 0 #define _FP_NANSIGN_D 0 #define _FP_NANSIGN_Q 0 @@ -166,48 +161,3 @@ void __sfp_handle_exceptions (int); # define strong_alias(name, aliasname) _strong_alias(name, aliasname) # define _strong_alias(name, aliasname) \ extern __typeof (name) aliasname __attribute__ ((alias (#name))); - -/* Add prototypes for the HFmode and BFmode functions. */ -typedef double DFtype2; -typedef float SFtype2; -typedef int DItype2 __attribute__ ((mode (DI))); -typedef unsigned int UDItype2 __attribute__ ((mode (DI))); -typedef int SItype2 __attribute__ ((mode (SI))); -typedef unsigned int USItype2 __attribute__ ((mode (SI))); - -#ifdef __FLOAT16__ -typedef float HFtype2 __attribute__ ((mode (HF))); - -extern CMPtype __eqhf2 (HFtype2, HFtype2); -extern DFtype2 __extendhfdf2 (HFtype2); -extern SFtype2 __extendhfsf2 (HFtype2); -extern DItype2 __fixhfdi (HFtype2); -extern SItype2 __fixhfsi (HFtype2); -extern UDItype2 __fixunshfdi (HFtype2); -extern USItype2 __fixunshfsi (HFtype2); -extern HFtype2 __floatdihf (DItype2); -extern HFtype2 __floatsihf (SItype2); -extern HFtype2 __floatundihf (UDItype2); -extern HFtype2 __floatunsihf (USItype2); -extern HFtype2 __truncdfhf2 (DFtype2); -extern HFtype2 __truncsfhf2 (SFtype2); -#endif - -#ifdef __BFLOAT16__ -typedef float BFtype2 __attribute__ ((mode (BF))); - -extern SFtype2 __extendbfsf2 (BFtype2); -extern BFtype2 __floatdibf (DItype2); -extern BFtype2 __floatsibf (SItype2); -extern BFtype2 __floatundibf (UDItype2); -extern BFtype2 __floatunsibf (USItype2); -extern BFtype2 __truncdfbf2 (DFtype2); -extern BFtype2 __truncsfbf2 (SFtype2); -#endif - -#if defined(__FLOAT16__) && defined(__BFLOAT16__) -extern HFtype2 __truncbfhf2 (BFtype2); -extern BFtype2 __trunchfbf2 (HFtype2); -#endif - - diff --git a/libgcc/config/rs6000/t-bfloat16 b/libgcc/config/rs6000/t-bfloat16 deleted file mode 100644 index cade2439c780..000000000000 --- a/libgcc/config/rs6000/t-bfloat16 +++ /dev/null @@ -1,30 +0,0 @@ -# __bfloat16 library support - -bfp16_funcs = extendbfsf2 floatdibf floatsibf floatundibf floatunsibf \ - truncdfbf2 truncsfbf2 - -bfp16_src = $(addprefix $(srcdir)/soft-fp/,$(addsuffix .c,$(bfp16_funcs))) -bfp16_obj = $(addsuffix $(objext),$(bfp16_funcs)) - -BFP16_CFLAGS = -mbfloat16 -Wno-psabi \ - -I$(srcdir)/soft-fp \ - -I$(srcdir)/config/rs6000 \ - -$(bfp16_obj) : INTERNAL_CFLAGS += $(BFP16_CFLAGS) - -# For now, only put it in the static library -# LIB2ADD += $(bfp16_src) - -LIB2ADD_ST += $(bfp16_src) - -.PHONY: test-bfloat16 clean-bfloat16 - -test-bfloat16: - @echo "bfp16_src:"; \ - for x in $(bfp16_src); do echo " $$x"; done; \ - echo; \ - echo "bfp16_obj:"; \ - for x in $(bfp16_obj); do echo " $$x"; done; - -clean-bfloat16: - @$(MULTICLEAN) multi-clean DO=clean-float16 diff --git a/libgcc/config/rs6000/t-both-fp16 b/libgcc/config/rs6000/t-both-fp16 deleted file mode 100644 index d51b7abbf086..000000000000 --- a/libgcc/config/rs6000/t-both-fp16 +++ /dev/null @@ -1,28 +0,0 @@ -# Conversion between __bfloat16 and _Float16 - -both_fp16_funcs = truncbfhf2 trunchfbf2 -both_fp16_src = $(addprefix $(srcdir)/soft-fp/,$(addsuffix .c,$(both_fp16_funcs))) -both_fp16_obj = $(addsuffix $(objext),$(both_fp16_funcs)) - -BOTH_FP16_CFLAGS = -mfloat16 -mbfloat16 -Wno-psabi \ - -I$(srcdir)/soft-fp \ - -I$(srcdir)/config/rs6000 \ - -$(both_fp16_obj) : INTERNAL_CFLAGS += $(BOTH_FP16_CFLAGS) - -# For now, only put it in the static library -# LIB2ADD += $(both_fp16_src) - -LIB2ADD_ST += $(both_fp16_src) - -.PHONY: test-both-fp16 clean-both-fp16 - -test-both-fp16: - @echo "both_fp16_src:"; \ - for x in $(both_fp16_src); do echo " $$x"; done; \ - echo; \ - echo "both_fp16_obj:"; \ - for x in $(both_fp16_obj); do echo " $$x"; done; - -clean-both-fp16: - @$(MULTICLEAN) multi-clean DO=clean-both-fp16 diff --git a/libgcc/config/rs6000/t-float16 b/libgcc/config/rs6000/t-float16 deleted file mode 100644 index f961097e85d1..000000000000 --- a/libgcc/config/rs6000/t-float16 +++ /dev/null @@ -1,31 +0,0 @@ -# _Float16 library support - -fp16_funcs = eqhf2 extendhfdf2 extendhfsf2 \ - fixhfdi fixhfsi fixunshfdi fixunshfsi \ - floatdihf floatsihf floatundihf floatunsihf \ - truncdfhf2 truncsfhf2 - -fp16_src = $(addprefix $(srcdir)/soft-fp/,$(addsuffix .c,$(fp16_funcs))) -fp16_obj = $(addsuffix $(objext),$(fp16_funcs)) - -FP16_CFLAGS = -mfloat16 -Wno-psabi \ - -I$(srcdir)/soft-fp -I$(srcdir)/config/rs6000 - -$(fp16_obj) : INTERNAL_CFLAGS += $(FP16_CFLAGS) - -# For now, only put it in the static library -# LIB2ADD += $(fp16_src) - -LIB2ADD_ST += $(fp16_src) - -.PHONY: test-float16 clean-float16 - -test-float16: - @echo "fp16_src:"; \ - for x in $(fp16_src); do echo " $$x"; done; \ - echo; \ - echo "fp16_obj:"; \ - for x in $(fp16_obj); do echo " $$x"; done; - -clean-float16: - @$(MULTICLEAN) multi-clean DO=clean-float16 diff --git a/libgcc/configure b/libgcc/configure index ed7ea9e7d621..d5e80d227ff6 100755 --- a/libgcc/configure +++ b/libgcc/configure @@ -5188,8 +5188,6 @@ case ${host} in # check if we have VSX (ISA 2.06) support to build the software libraries, and # whether the assembler can handle xsaddqp for hardware support. Also check if # a new glibc is being used so that __builtin_cpu_supports can be used. -# -# Add float16 support also powerpc*-*-linux*) saved_CFLAGS="$CFLAGS" CFLAGS="$CFLAGS -mabi=altivec -mvsx -mfloat128" @@ -5284,48 +5282,6 @@ fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_powerpc_3_1_float128_hw" >&5 $as_echo "$libgcc_cv_powerpc_3_1_float128_hw" >&6; } CFLAGS="$saved_CFLAGS" - - CFLAGS="$CFLAGS -mfloat16 -Wno-psabi" - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the PowerPC can build the _Float16 libraries" >&5 -$as_echo_n "checking whether the PowerPC can build the _Float16 libraries... " >&6; } -if ${libgcc_cv_powerpc_float16+:} false; then : - $as_echo_n "(cached) " >&6 -else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -/* end confdefs.h. */ -_Float16 addf16 (_Float16 a, _Float16 b) { return a + b; } -_ACEOF -if ac_fn_c_try_compile "$LINENO"; then : - libgcc_cv_powerpc_float16=yes -else - libgcc_cv_powerpc_float16=no -fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext -fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_powerpc_float16" >&5 -$as_echo "$libgcc_cv_powerpc_float16" >&6; } - CFLAGS="$saved_CFLAGS" - - CFLAGS="$CFLAGS -mbfloat16 -Wno-psabi" - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the PowerPC can build __bfloat16 libraries" >&5 -$as_echo_n "checking whether the PowerPC can build __bfloat16 libraries... " >&6; } -if ${libgcc_cv_powerpc_bfloat16+:} false; then : - $as_echo_n "(cached) " >&6 -else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -/* end confdefs.h. */ -__bfloat16 addbf16 (__bfloat16 a, __bfloat16 b) { return a + b; } -_ACEOF -if ac_fn_c_try_compile "$LINENO"; then : - libgcc_cv_powerpc_bfloat16=yes -else - libgcc_cv_powerpc_bfloat16=no -fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext -fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_powerpc_bfloat16" >&5 -$as_echo "$libgcc_cv_powerpc_bfloat16" >&6; } - CFLAGS="$saved_CFLAGS" esac # Collect host-machine-specific information. diff --git a/libgcc/configure.ac b/libgcc/configure.ac index 464acdee14c3..65cd3c6aa1a5 100644 --- a/libgcc/configure.ac +++ b/libgcc/configure.ac @@ -407,8 +407,6 @@ case ${host} in # check if we have VSX (ISA 2.06) support to build the software libraries, and # whether the assembler can handle xsaddqp for hardware support. Also check if # a new glibc is being used so that __builtin_cpu_supports can be used. -# -# Add float16 support also powerpc*-*-linux*) saved_CFLAGS="$CFLAGS" CFLAGS="$CFLAGS -mabi=altivec -mvsx -mfloat128" @@ -467,24 +465,6 @@ powerpc*-*-linux*) [libgcc_cv_powerpc_3_1_float128_hw=yes], [libgcc_cv_powerpc_3_1_float128_hw=no])]) CFLAGS="$saved_CFLAGS" - - CFLAGS="$CFLAGS -mfloat16 -Wno-psabi" - AC_CACHE_CHECK([whether the PowerPC can build the _Float16 libraries], - [libgcc_cv_powerpc_float16], - [AC_COMPILE_IFELSE( - [AC_LANG_SOURCE([_Float16 addf16 (_Float16 a, _Float16 b) { return a + b; }])], - [libgcc_cv_powerpc_float16=yes], - [libgcc_cv_powerpc_float16=no])]) - CFLAGS="$saved_CFLAGS" - - CFLAGS="$CFLAGS -mbfloat16 -Wno-psabi" - AC_CACHE_CHECK([whether the PowerPC can build __bfloat16 libraries], - [libgcc_cv_powerpc_bfloat16], - [AC_COMPILE_IFELSE( - [AC_LANG_SOURCE([__bfloat16 addbf16 (__bfloat16 a, __bfloat16 b) { return a + b; }])], - [libgcc_cv_powerpc_bfloat16=yes], - [libgcc_cv_powerpc_bfloat16=no])]) - CFLAGS="$saved_CFLAGS" esac # Collect host-machine-specific information.
