https://gcc.gnu.org/g:901df1b412fc463944625cf94186c49bb0b24e2e
commit 901df1b412fc463944625cf94186c49bb0b24e2e Author: Michael Meissner <[email protected]> Date: Mon Oct 27 19:55:06 2025 -0400 Reaarange code to match future patch submission. 2025-10-27 Michael Meissner <[email protected]> gcc/ * config/rs6000/float16.md (neg<mode>2): Move code around to match future patch submission. (abs<mode>2): Likewise. (nabs<mode>2): Likewise. (and<mode>3): Likewise. (ior<mode>3): Likewise. (xor<mode>3): Likewise. (nor<mode>3): Likewise. (andn<mode>3): Likewise. (eqv<mode>3): Likewise. (nand<mode>3"): Likewise. (iorn<mode>3): Likewise. (bool<mode>3): Likewise. (boolc<mode>3): Likewise. (boolcc<mode>3): Likewise. Diff: --- gcc/config/rs6000/float16.md | 299 +++++++++++++++++++++++++++++-------------- 1 file changed, 202 insertions(+), 97 deletions(-) diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md index 1365086f5751..1a63c6d73bd3 100644 --- a/gcc/config/rs6000/float16.md +++ b/gcc/config/rs6000/float16.md @@ -595,6 +595,208 @@ DONE; }) +;; Negate 16-bit floating point by XOR with -0.0. + +(define_insn_and_split "neg<mode>2" + [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr") + (neg:FP16 (match_operand:FP16 1 "gpc_reg_operand" "wa,wr"))) + (clobber (match_scratch:FP16 2 "=&wa,&r"))] + "" + "#" + "&& 1" + [(set (match_dup 2) + (match_dup 3)) + (set (match_dup 0) + (xor:FP16 (match_dup 1) + (match_dup 2)))] +{ + if (GET_CODE (operands[2]) == SCRATCH) + operands[2] = gen_reg_rtx (<MODE>mode); + + REAL_VALUE_TYPE dconst; + + gcc_assert (real_from_string (&dconst, "-0.0") == 0); + + rtx rc = const_double_from_real_value (dconst, <MODE>mode); + if (!TARGET_PREFIXED) + rc = force_const_mem (<MODE>mode, rc); + + operands[3] = rc; +} + [(set_attr "type" "veclogical,integer") + (set_attr "length" "16")]) + +;; 16-bit floating point absolute value + +(define_insn_and_split "abs<mode>2" + [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr") + (abs:FP16 + (match_operand:FP16 1 "gpc_reg_operand" "wa,wr"))) + (clobber (match_scratch:FP16 2 "=&wa,&r"))] + "" + "#" + "&& 1" + [(set (match_dup 2) + (match_dup 3)) + (set (match_dup 0) + (and:FP16 (match_dup 1) + (not:FP16 (match_dup 2))))] +{ + if (GET_CODE (operands[2]) == SCRATCH) + operands[2] = gen_reg_rtx (<MODE>mode); + + REAL_VALUE_TYPE dconst; + + gcc_assert (real_from_string (&dconst, "-0.0") == 0); + + rtx rc = const_double_from_real_value (dconst, <MODE>mode); + + if (!TARGET_PREFIXED) + rc = force_const_mem (<MODE>mode, rc); + + operands[3] = rc; +} + [(set_attr "type" "veclogical,integer") + (set_attr "length" "16")]) + +;; 16-bit negative floating point absolute value + +(define_insn_and_split "*nabs<mode>2" + [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr") + (neg:FP16 + (abs:FP16 + (match_operand:FP16 1 "gpc_reg_operand" "wa,wr")))) + (clobber (match_scratch:FP16 2 "=&wa,&r"))] + "" + "#" + "&& 1" + [(set (match_dup 2) + (match_dup 3)) + (set (match_dup 0) + (ior:FP16 (match_dup 1) + (match_dup 2)))] +{ + if (GET_CODE (operands[2]) == SCRATCH) + operands[2] = gen_reg_rtx (<MODE>mode); + + REAL_VALUE_TYPE dconst; + + gcc_assert (real_from_string (&dconst, "-0.0") == 0); + rtx rc = const_double_from_real_value (dconst, <MODE>mode); + + if (!TARGET_PREFIXED) + rc = force_const_mem (<MODE>mode, rc); + + operands[3] = rc; +} + [(set_attr "type" "veclogical,integer") + (set_attr "length" "16")]) + +;; Add logical operations for 16-bit floating point types that are used +;; for things like negate, abs, and negative abs. Possibly in the +;; future we might need logical operators for extracting exponents and +;; mantissas. +(define_expand "and<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand") + (and:FP16 (match_operand:FP16 1 "gpc_reg_operand") + (match_operand:FP16 2 "gpc_reg_operand")))] + "" + "") + +(define_expand "ior<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand") + (ior:FP16 (match_operand:FP16 1 "gpc_reg_operand") + (match_operand:FP16 2 "gpc_reg_operand")))] + "" + "") + +(define_expand "xor<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand") + (xor:FP16 (match_operand:FP16 1 "gpc_reg_operand") + (match_operand:FP16 2 "gpc_reg_operand")))] + "" + "") + +(define_expand "nor<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand") + (and:FP16 + (not:FP16 (match_operand:FP16 1 "gpc_reg_operand")) + (not:FP16 (match_operand:FP16 2 "gpc_reg_operand"))))] + "" + "") + +(define_expand "andn<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand") + (and:FP16 + (not:FP16 (match_operand:FP16 2 "gpc_reg_operand")) + (match_operand:FP16 1 "gpc_reg_operand")))] + "" + "") + +(define_expand "eqv<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand") + (not:FP16 + (xor:FP16 (match_operand:FP16 1 "gpc_reg_operand") + (match_operand:FP16 2 "gpc_reg_operand"))))] + "" + "") + +;; Rewrite nand into canonical form +(define_expand "nand<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand") + (ior:FP16 + (not:FP16 (match_operand:FP16 1 "gpc_reg_operand")) + (not:FP16 (match_operand:FP16 2 "gpc_reg_operand"))))] + "" + "") + +;; The canonical form is to have the negated element first, so we need to +;; reverse arguments. +(define_expand "iorn<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand") + (ior:FP16 + (not:FP16 (match_operand:FP16 2 "gpc_reg_operand")) + (match_operand:FP16 1 "gpc_reg_operand")))] + "" + "") + +;; AND, IOR, and XOR insns. Unlike HImode operations prefer using +;; floating point/vector registers over GPRs. +(define_insn "*bool<mode>3" + [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,r") + (match_operator:FP16 3 "boolean_operator" + [(match_operand:FP16 1 "gpc_reg_operand" "wa,r") + (match_operand:FP16 2 "gpc_reg_operand" "wa,r")]))] + "" + "@ + xxl%q3 %x0,%x1,%x2 + %q3 %0,%1,%2" + [(set_attr "type" "veclogical,logical")]) + +;; ANDC, IORC, and EQV insns. +(define_insn "*boolc<mode>3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=wa,r") + (match_operator:GPR 3 "boolean_operator" + [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "wa,r")) + (match_operand:GPR 1 "gpc_reg_operand" "wa,r")]))] + "" + "@ + xxl%q3 %x0,%x1,%x0 + %q3 %0,%1,%2" + [(set_attr "type" "veclogical,logical")]) + +;; NOR and NAND insns. +(define_insn "*boolcc<mode>3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=wa,r") + (match_operator:GPR 3 "boolean_operator" + [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "wa,r")) + (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "wa,r"))]))] + "" + "@ + xxl%q3 %x0,%x1,%x2 + %q3 %0,%1,%2" + [(set_attr "type" "veclogical,logical")]) + ;; Optimize __bfloat16 binary operations. Unlike _Float16 where we ;; have instructions to convert between HFmode and SFmode as scalar ;; values, with BFmode, we only have vector conversions. Thus to do: @@ -1012,103 +1214,6 @@ || peep2_reg_dead_p (1, operands[1])" [(set (match_dup 2) (match_dup 1))]) -;; Negate 16-bit floating point by XOR with -0.0. - -(define_insn_and_split "neg<mode>2" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr") - (neg:FP16 (match_operand:FP16 1 "gpc_reg_operand" "wa,wr"))) - (clobber (match_scratch:FP16 2 "=&wa,&r"))] - "" - "#" - "&& 1" - [(set (match_dup 2) - (match_dup 3)) - (set (match_dup 0) - (xor:FP16 (match_dup 1) - (match_dup 2)))] -{ - if (GET_CODE (operands[2]) == SCRATCH) - operands[2] = gen_reg_rtx (<MODE>mode); - - REAL_VALUE_TYPE dconst; - - gcc_assert (real_from_string (&dconst, "-0.0") == 0); - - rtx rc = const_double_from_real_value (dconst, <MODE>mode); - if (!TARGET_PREFIXED) - rc = force_const_mem (<MODE>mode, rc); - - operands[3] = rc; -} - [(set_attr "type" "veclogical,integer") - (set_attr "length" "16")]) - -;; 16-bit floating point absolute value - -(define_insn_and_split "abs<mode>2" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr") - (abs:FP16 - (match_operand:FP16 1 "gpc_reg_operand" "wa,wr"))) - (clobber (match_scratch:FP16 2 "=&wa,&r"))] - "" - "#" - "&& 1" - [(set (match_dup 2) - (match_dup 3)) - (set (match_dup 0) - (and:FP16 (match_dup 1) - (not:FP16 (match_dup 2))))] -{ - if (GET_CODE (operands[2]) == SCRATCH) - operands[2] = gen_reg_rtx (<MODE>mode); - - REAL_VALUE_TYPE dconst; - - gcc_assert (real_from_string (&dconst, "-0.0") == 0); - - rtx rc = const_double_from_real_value (dconst, <MODE>mode); - - if (!TARGET_PREFIXED) - rc = force_const_mem (<MODE>mode, rc); - - operands[3] = rc; -} - [(set_attr "type" "veclogical,integer") - (set_attr "length" "16")]) - -;; 16-bit negative floating point absolute value - -(define_insn_and_split "*nabs<mode>2" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr") - (neg:FP16 - (abs:FP16 - (match_operand:FP16 1 "gpc_reg_operand" "wa,wr")))) - (clobber (match_scratch:FP16 2 "=&wa,&r"))] - "" - "#" - "&& 1" - [(set (match_dup 2) - (match_dup 3)) - (set (match_dup 0) - (ior:FP16 (match_dup 1) - (match_dup 2)))] -{ - if (GET_CODE (operands[2]) == SCRATCH) - operands[2] = gen_reg_rtx (<MODE>mode); - - REAL_VALUE_TYPE dconst; - - gcc_assert (real_from_string (&dconst, "-0.0") == 0); - rtx rc = const_double_from_real_value (dconst, <MODE>mode); - - if (!TARGET_PREFIXED) - rc = force_const_mem (<MODE>mode, rc); - - operands[3] = rc; -} - [(set_attr "type" "veclogical,integer") - (set_attr "length" "16")]) - ;; Vector Pack support. (define_expand "vec_pack_trunc_v4sf_v8hf"
