https://gcc.gnu.org/g:befc050c705a7ddcf3336920cd8fd327ef2ecb41
commit befc050c705a7ddcf3336920cd8fd327ef2ecb41 Author: Michael Meissner <[email protected]> Date: Mon Oct 27 21:32:59 2025 -0400 Revert changes Diff: --- gcc/config.gcc | 1 - gcc/config/rs6000/float16.cc | 185 --------- gcc/config/rs6000/float16.md | 775 ------------------------------------- gcc/config/rs6000/rs6000-protos.h | 13 - gcc/config/rs6000/rs6000.h | 10 - gcc/config/rs6000/t-rs6000 | 4 - libgcc/config.host | 12 - libgcc/config/rs6000/sfp-machine.h | 50 --- libgcc/config/rs6000/t-bfloat16 | 30 -- libgcc/config/rs6000/t-both-fp16 | 28 -- libgcc/config/rs6000/t-float16 | 31 -- libgcc/configure | 44 --- libgcc/configure.ac | 20 - 13 files changed, 1203 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index d6d4d06c3107..a753c018ae1c 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -533,7 +533,6 @@ powerpc*-*-*) extra_objs="rs6000-string.o rs6000-p8swap.o rs6000-logue.o" extra_objs="${extra_objs} rs6000-call.o rs6000-pcrel-opt.o" extra_objs="${extra_objs} rs6000-builtins.o rs6000-builtin.o" - extra_objs="${extra_objs} float16.o" extra_headers="ppc-asm.h altivec.h htmintrin.h htmxlintrin.h" extra_headers="${extra_headers} bmi2intrin.h bmiintrin.h" extra_headers="${extra_headers} xmmintrin.h mm_malloc.h emmintrin.h" diff --git a/gcc/config/rs6000/float16.cc b/gcc/config/rs6000/float16.cc deleted file mode 100644 index 5274a0df962f..000000000000 --- a/gcc/config/rs6000/float16.cc +++ /dev/null @@ -1,185 +0,0 @@ -/* Subroutines for the C front end on the PowerPC architecture. - Copyright (C) 2002-2025 Free Software Foundation, Inc. - - Contributed by Zack Weinberg <[email protected]> - and Paolo Bonzini <[email protected]> - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 3, or (at your - option) any later version. - - GCC is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING3. If not see - <http://www.gnu.org/licenses/>. */ - -/* 16-bit floating point support. */ - -#include "config.h" -#include "system.h" -#include "coretypes.h" -#include "backend.h" -#include "rtl.h" -#include "tree.h" -#include "memmodel.h" -#include "tm_p.h" -#include "stringpool.h" -#include "expmed.h" -#include "optabs.h" -#include "regs.h" -#include "insn-attr.h" -#include "flags.h" -#include "attribs.h" -#include "explow.h" -#include "expr.h" -#include "common/common-target.h" -#include "rs6000-internal.h" - -/* Expand a 16-bit vector operation: - - ICODE: Operation to perform. - RESULT: Result of the operation. - OP1: Input operand1. - OP2: Input operand2. - OP3: Input operand3 or NULL_RTX. - SUBTYPE: Describe the operation. */ - -void -fp16_vectorization (enum rtx_code icode, - rtx result, - rtx op1, - rtx op2, - rtx op3, - enum fp16_operation subtype) -{ - gcc_assert (can_create_pseudo_p ()); - - machine_mode result_mode = GET_MODE (result); - rtx op_orig[3] = { op1, op2, op3 }; - rtx op_hi[3]; - rtx op_lo[3]; - rtx result_hi; - rtx result_lo; - size_t n_opts; - - switch (subtype) - { - case FP16_BINARY: - n_opts = 2; - break; - - case FP16_FMA: - case FP16_FMS: - case FP16_NFMA: - case FP16_NFMS: - n_opts = 3; - break; - - default: - gcc_unreachable (); - } - - /* Allocate 2 temporaries for the results and the input operands. */ - result_hi = gen_reg_rtx (V4SFmode); - result_lo = gen_reg_rtx (V4SFmode); - - for (size_t i = 0; i < n_opts; i++) - { - gcc_assert (op_orig[i] != NULL_RTX); - op_hi[i] = gen_reg_rtx (V4SFmode); /* high register. */ - op_lo[i] = gen_reg_rtx (V4SFmode); /* low register. */ - - rtx interleave_hi = gen_reg_rtx (result_mode); - rtx interleave_lo = gen_reg_rtx (result_mode); - rtx orig = op_orig[i]; - - rs6000_expand_interleave (interleave_hi, orig, orig, !BYTES_BIG_ENDIAN); - rs6000_expand_interleave (interleave_lo, orig, orig, BYTES_BIG_ENDIAN); - - if (result_mode == V8HFmode) - { - emit_insn (gen_xvcvhpsp_v8hf (op_hi[i], interleave_hi)); - emit_insn (gen_xvcvhpsp_v8hf (op_lo[i], interleave_lo)); - } - - else if (result_mode == V8BFmode) - { - emit_insn (gen_xvcvbf16spn_v8bf (op_hi[i], interleave_hi)); - emit_insn (gen_xvcvbf16spn_v8bf (op_lo[i], interleave_lo)); - } - - else - gcc_unreachable (); - } - - /* Do 2 sets of V4SFmode operations. */ - switch (subtype) - { - case FP16_BINARY: - emit_insn (gen_rtx_SET (result_hi, - gen_rtx_fmt_ee (icode, V4SFmode, - op_hi[0], - op_hi[1]))); - - emit_insn (gen_rtx_SET (result_lo, - gen_rtx_fmt_ee (icode, V4SFmode, - op_lo[0], - op_lo[1]))); - break; - - case FP16_FMA: - case FP16_FMS: - case FP16_NFMA: - case FP16_NFMS: - { - rtx op1_hi = op_hi[0]; - rtx op2_hi = op_hi[1]; - rtx op3_hi = op_hi[2]; - - rtx op1_lo = op_lo[0]; - rtx op2_lo = op_lo[1]; - rtx op3_lo = op_lo[2]; - - if (subtype == FP16_FMS || subtype == FP16_NFMS) - { - op3_hi = gen_rtx_NEG (V4SFmode, op3_hi); - op3_lo = gen_rtx_NEG (V4SFmode, op3_lo); - } - - rtx op_fma_hi = gen_rtx_FMA (V4SFmode, op1_hi, op2_hi, op3_hi); - rtx op_fma_lo = gen_rtx_FMA (V4SFmode, op1_lo, op2_lo, op3_lo); - - if (subtype == FP16_NFMA || subtype == FP16_NFMS) - { - op_fma_hi = gen_rtx_NEG (V4SFmode, op_fma_hi); - op_fma_lo = gen_rtx_NEG (V4SFmode, op_fma_lo); - } - - emit_insn (gen_rtx_SET (result_hi, op_fma_hi)); - emit_insn (gen_rtx_SET (result_lo, op_fma_lo)); - } - break; - - default: - gcc_unreachable (); - } - - /* Combine the 2 V4SFmode operations into one V8HFmode/V8BFmode vector. */ - if (result_mode == V8HFmode) - emit_insn (gen_vec_pack_trunc_v4sf_v8hf (result, result_hi, result_lo)); - - else if (result_mode == V8BFmode) - emit_insn (gen_vec_pack_trunc_v4sf_v8bf (result, result_hi, result_lo)); - - else - gcc_unreachable (); - - return; -} diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md index 417806296548..d186d8e7d601 100644 --- a/gcc/config/rs6000/float16.md +++ b/gcc/config/rs6000/float16.md @@ -25,25 +25,6 @@ (define_mode_iterator FP16 [(BF "TARGET_BFLOAT16") (HF "TARGET_FLOAT16")]) -;; Mode iterator for 16-bit floating point modes on machines with -;; hardware support both as a scalar and as a vector. -(define_mode_iterator FP16_HW [(BF "TARGET_BFLOAT16_HW") - (HF "TARGET_FLOAT16_HW")]) - -(define_mode_iterator VFP16_HW [(V8BF "TARGET_BFLOAT16_HW") - (V8HF "TARGET_FLOAT16_HW")]) - -;; Mode iterator for floating point modes other than SF/DFmode that we -;; convert to/from _Float16 (HFmode) via DFmode. -(define_mode_iterator fp16_float_convert [TF KF IF SD DD TD]) - -;; Mode attribute giving the instruction to convert the even -;; V8HFmode or V8BFmode elements to V4SFmode -(define_mode_attr cvt_fp16_to_v4sf_insn [(BF "xvcvbf16spn") - (HF "xvcvhpsp") - (V8BF "xvcvbf16spn") - (V8HF "xvcvhpsp")]) - ;; Mode attribute giving the vector mode for a 16-bit floating point ;; scalar in both upper and lower case. (define_mode_attr FP16_VECTOR8 [(BF "V8BF") @@ -51,35 +32,6 @@ (define_mode_attr fp16_vector8 [(BF "v8bf") (HF "v8hf")]) - -;; Mode attribute giving the vector mode with 4 16-bit floating point -;; elements given a scalar or 8 element vector. -(define_mode_attr FP16_VECTOR4 [(BF "V4BF") - (HF "V4HF") - (V8BF "V4BF") - (V8HF "V4HF")]) - -;; Binary operators for bfloat16/float16 vectorization. -(define_code_iterator FP16_BINARY_OP [plus minus mult smax smin]) - -;; Standard names for the unary/binary/ternary operators -(define_code_attr fp16_names [(abs "abs") - (fma "fma") - (plus "add") - (minus "sub") - (mult "mul") - (neg "neg") - (smax "smax") - (smin "smin")]) - -;; UNSPEC constants -(define_c_enum "unspec" - [UNSPEC_FP16_SHIFT_LEFT_32BIT - UNSPEC_CVT_FP16_TO_V4SF - UNSPEC_XXSPLTW_FP16 - UNSPEC_XVCVSPBF16_BF - UNSPEC_XVCVSPHP_V8HF - UNSPEC_XVCVSPBF16_V8BF]) ;; _Float16 and __bfloat16 moves (define_expand "mov<mode>" @@ -170,730 +122,3 @@ } [(set_attr "type" "veclogical,vecperm") (set_attr "prefixed" "*,yes")]) - -;; Convert IEEE 16-bit floating point to/from other floating point modes. - -(define_insn "extendhf<mode>2" - [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa") - (float_extend:SFDF - (match_operand:HF 1 "vsx_register_operand" "wa")))] - "TARGET_FLOAT16_HW" - "xscvhpdp %x0,%x1" - [(set_attr "type" "fpsimple")]) - -(define_insn "trunc<mode>hf2" - [(set (match_operand:HF 0 "vsx_register_operand" "=wa") - (float_truncate:HF - (match_operand:SFDF 1 "vsx_register_operand" "wa")))] - "TARGET_FLOAT16_HW" - "xscvdphp %x0,%x1" - [(set_attr "type" "fpsimple")]) - -;; Convert BFmode to SFmode/DFmode. -;; 3 instructions are generated: -;; VSPLTH -- duplicate BFmode into all elements -;; XVCVBF16SPN -- convert even BFmode elements to SFmode -;; XSCVSPNDP -- convert memory format of SFmode to DFmode. -(define_insn_and_split "extendbf<mode>2" - [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa") - (float_extend:SFDF - (match_operand:BF 1 "vsx_register_operand" "v"))) - (clobber (match_scratch:V8BF 2 "=v"))] - "TARGET_BFLOAT16_HW" - "#" - "&& 1" - [(pc)] -{ - rtx op0 = operands[0]; - rtx op1 = operands[1]; - rtx op2_v8bf = operands[2]; - - if (GET_CODE (op2_v8bf) == SCRATCH) - op2_v8bf = gen_reg_rtx (V8BFmode); - - rtx op2_v4sf = gen_lowpart (V4SFmode, op2_v8bf); - - /* XXSLDWI -- shift BFmode element into the upper 32 bits. */ - emit_insn (gen_v8bf_shift_left_32bit (op2_v8bf, op1)); - - /* XVCVBF16SPN -- convert even V8BFmode elements to V4SFmode. */ - emit_insn (gen_cvt_fp16_to_v4sf_v8bf (op2_v4sf, op2_v8bf)); - - /* XSCVSPNDP -- convert single V4SFmode element to DFmode. */ - emit_insn (GET_MODE (op0) == SFmode - ? gen_xscvspdpn_sf (op0, op2_v4sf) - : gen_vsx_xscvspdpn (op0, op2_v4sf)); - - DONE; -} - [(set_attr "type" "fpsimple") - (set_attr "length" "12")]) - -;; Convert a SFmode scalar represented as DFmode to elements 0 and 1 of -;; V4SFmode. -(define_insn "xscvdpspn_sf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVSPDP))] - "VECTOR_UNIT_VSX_P (SFmode)" - "xscvdpspn %x0,%x1" - [(set_attr "type" "fp")]) - -;; Convert element 0 of a V4SFmode to scalar SFmode (which on the -;; PowerPC uses the DFmode encoding). -(define_insn "xscvspdpn_sf" - [(set (match_operand:SF 0 "vsx_register_operand" "=wa") - (unspec:SF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVSPDPN))] - "TARGET_XSCVSPDPN" - "xscvspdpn %x0,%x1" - [(set_attr "type" "fp")]) - -;; Vector shift left by 32 bits to get the 16-bit floating point value -;; into the upper 32 bits for the conversion. -(define_insn "<fp16_vector8>_shift_left_32bit" - [(set (match_operand:<FP16_VECTOR8> 0 "vsx_register_operand" "=wa") - (unspec:<FP16_VECTOR8> - [(match_operand:FP16_HW 1 "vsx_register_operand" "wa")] - UNSPEC_FP16_SHIFT_LEFT_32BIT))] - "" - "xxsldwi %x0,%x1,%x1,1" - [(set_attr "type" "vecperm")]) - -;; Convert SFmode/DFmode to BFmode. -;; 2 instructions are generated: -;; XSCVDPSPN -- convert SFmode/DFmode scalar to V4SFmode -;; XVCVSPBF16 -- convert V4SFmode to even V8BFmode - -(define_insn_and_split "trunc<mode>bf2" - [(set (match_operand:BF 0 "vsx_register_operand" "=wa") - (float_truncate:BF - (match_operand:SFDF 1 "vsx_register_operand" "wa"))) - (clobber (match_scratch:V4SF 2 "=wa"))] - "TARGET_BFLOAT16_HW" - "#" - "&& 1" - [(pc)] -{ - rtx op0 = operands[0]; - rtx op1 = operands[1]; - rtx op2 = operands[2]; - - if (GET_CODE (op2) == SCRATCH) - op2 = gen_reg_rtx (V4SFmode); - - emit_insn (GET_MODE (op1) == SFmode - ? gen_xscvdpspn_sf (op2, op1) - : gen_vsx_xscvdpspn (op2, op1)); - - emit_insn (gen_xvcvspbf16_bf (op0, op2)); - DONE; -} - [(set_attr "type" "fpsimple")]) - -(define_insn "vsx_xscvdpspn_sf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVDPSPN))] - "TARGET_XSCVDPSPN" - "xscvdpspn %x0,%x1" - [(set_attr "type" "fp")]) - -;; Convert the even elements of a vector 16-bit floating point to -;; V4SFmode. Deal with little endian vs. big endian element ordering -;; in identifying which elements are converted. - -(define_expand "cvt_fp16_to_v4sf_<mode>" - [(set (match_operand:V4SF 0 "vsx_register_operand") - (float_extend:V4SF - (vec_select:<FP16_VECTOR4> - (match_operand:VFP16_HW 1 "vsx_register_operand") - (parallel [(match_dup 2) - (match_dup 3) - (match_dup 4) - (match_dup 5)]))))] - "" -{ - int endian_adjust = WORDS_BIG_ENDIAN ? 0 : 1; - operands[2] = GEN_INT (0 + endian_adjust); - operands[3] = GEN_INT (2 + endian_adjust); - operands[4] = GEN_INT (4 + endian_adjust); - operands[5] = GEN_INT (6 + endian_adjust); -}) - -(define_insn "*cvt_fp16_to_v4sf_<mode>_le" - [(set (match_operand:V4SF 0 "vsx_register_operand") - (float_extend:V4SF - (vec_select:<FP16_VECTOR4> - (match_operand:VFP16_HW 1 "vsx_register_operand") - (parallel [(const_int 1) - (const_int 3) - (const_int 5) - (const_int 7)]))))] - "!WORDS_BIG_ENDIAN" - "<cvt_fp16_to_v4sf_insn> %x0,%x1" - [(set_attr "type" "vecfloat")]) - -(define_insn "*cvt_fp16_to_v4sf_<mode>_be" - [(set (match_operand:V4SF 0 "vsx_register_operand") - (float_extend:V4SF - (vec_select:<FP16_VECTOR4> - (match_operand:VFP16_HW 1 "vsx_register_operand") - (parallel [(const_int 0) - (const_int 2) - (const_int 4) - (const_int 6)]))))] - "WORDS_BIG_ENDIAN" - "<cvt_fp16_to_v4sf_insn> %x0,%x1" - [(set_attr "type" "vecfloat")]) - -;; Duplicate and convert a 16-bit floating point scalar to V4SFmode. - -(define_insn_and_split "*dup_<mode>_to_v4sf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (vec_duplicate:V4SF - (float_extend:SF - (match_operand:FP16_HW 1 "vsx_register_operand" "wa"))))] - "" - "#" - "&& 1" - [(pc)] -{ - rtx op0 = operands[0]; - rtx op1 = operands[1]; - rtx op0_vfp16 = gen_lowpart (<FP16_VECTOR8>mode, op0); - - emit_insn (gen_xxspltw_<mode> (op0, op1)); - emit_insn (gen_cvt_fp16_to_v4sf_<fp16_vector8> (op0, op0_vfp16)); - DONE; -} - [(set_attr "length" "8") - (set_attr "type" "vecperm")]) - -;; Duplicate a HF/BF value so it can be used for xvcvhpspn/xvcvbf16spn. -;; Because xvcvhpspn/xvcvbf16spn only uses the even elements, we can -;; use xxspltw instead of vspltw. This has the advantage that the -;; register allocator can use any of the 64 VSX registers instead of -;; being limited to the 32 Altivec registers that VSPLTH would require. - -(define_insn "xxspltw_<mode>" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:FP16_HW 1 "vsx_register_operand" "wa")] - UNSPEC_XXSPLTW_FP16))] - "" - "xxspltw %x0,%x1,1" - [(set_attr "type" "vecperm")]) - -;; Convert a bfloat16 floating point scalar that has been splatted to -;; V4SFmode. - -(define_insn "xvcvbf16spn_bf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_CVT_FP16_TO_V4SF))] - "TARGET_BFLOAT16_HW" - "xvcvbf16spn %x0,%x1" - [(set_attr "type" "vecperm")]) - -;; Convert a V4SFmode vector to a 16-bit floating point scalar. We -;; only care about the 2nd V4SFmode element, which is the element we -;; converted the 16-bit scalar (4th element) to V4SFmode to do the -;; operation, and converted it back. - -(define_insn "xvcvspbf16_bf" - [(set (match_operand:BF 0 "vsx_register_operand" "=wa") - (unspec:BF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_XVCVSPBF16_BF))] - "TARGET_BFLOAT16_HW" - "xvcvspbf16 %x0,%x1" - [(set_attr "type" "vecfloat")]) - -;; Convert between HFmode/BFmode and 128-bit binary floating point and -;; decimal floating point types. We use convert_move since some of the -;; types might not have valid RTX expanders. We use DFmode as the -;; intermediate conversion destination. - -(define_expand "extend<FP16_HW:mode><fp16_float_convert:mode>2" - [(set (match_operand:fp16_float_convert 0 "vsx_register_operand") - (float_extend:fp16_float_convert - (match_operand:FP16_HW 1 "vsx_register_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - emit_insn (gen_extend<FP16_HW:mode>df2 (df_tmp, operands[1])); - convert_move (operands[0], df_tmp, 0); - DONE; -}) - -(define_expand "trunc<fp16_float_convert:mode><FP16_HW:mode>2" - [(set (match_operand:FP16_HW 0 "vsx_register_operand") - (float_truncate:FP16_HW - (match_operand:fp16_float_convert 1 "vsx_register_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - - convert_move (df_tmp, operands[1], 0); - emit_insn (gen_truncdf<FP16_HW:mode>2 (operands[0], df_tmp)); - DONE; -}) - -;; Convert integers to 16-bit floating point modes. -(define_expand "float<GPR:mode><FP16_HW:mode>2" - [(set (match_operand:FP16_HW 0 "vsx_register_operand") - (float:FP16_HW - (match_operand:GPR 1 "nonimmediate_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - emit_insn (gen_float<GPR:mode>df2 (df_tmp, operands[1])); - emit_insn (gen_truncdf<FP16_HW:mode>2 (operands[0], df_tmp)); - DONE; -}) - -(define_expand "floatuns<GPR:mode><FP16_HW:mode>2" - [(set (match_operand:FP16_HW 0 "vsx_register_operand") - (unsigned_float:FP16_HW - (match_operand:GPR 1 "nonimmediate_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - emit_insn (gen_floatuns<GPR:mode>df2 (df_tmp, operands[1])); - emit_insn (gen_truncdf<FP16_HW:mode>2 (operands[0], df_tmp)); - DONE; -}) - -;; Convert 16-bit floating point modes to integers -(define_expand "fix_trunc<FP16_HW:mode><GPR:mode>2" - [(set (match_operand:GPR 0 "vsx_register_operand") - (fix:GPR - (match_operand:FP16_HW 1 "vsx_register_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - emit_insn (gen_extend<FP16_HW:mode>df2 (df_tmp, operands[1])); - emit_insn (gen_fix_truncdf<GPR:mode>2 (operands[0], df_tmp)); - DONE; -}) - -(define_expand "fixuns_trunc<FP16_HW:mode><GPR:mode>2" - [(set (match_operand:GPR 0 "vsx_register_operand") - (unsigned_fix:GPR - (match_operand:FP16_HW 1 "vsx_register_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - emit_insn (gen_extend<FP16_HW:mode>df2 (df_tmp, operands[1])); - emit_insn (gen_fixuns_truncdf<GPR:mode>2 (operands[0], df_tmp)); - DONE; -}) - -;; Negate 16-bit floating point by XOR with -0.0. - -(define_insn_and_split "neg<mode>2" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr") - (neg:FP16 (match_operand:FP16 1 "gpc_reg_operand" "wa,wr"))) - (clobber (match_scratch:FP16 2 "=&wa,&r"))] - "" - "#" - "&& 1" - [(set (match_dup 2) - (match_dup 3)) - (set (match_dup 0) - (xor:FP16 (match_dup 1) - (match_dup 2)))] -{ - if (GET_CODE (operands[2]) == SCRATCH) - operands[2] = gen_reg_rtx (<MODE>mode); - - REAL_VALUE_TYPE dconst; - - gcc_assert (real_from_string (&dconst, "-0.0") == 0); - - rtx rc = const_double_from_real_value (dconst, <MODE>mode); - if (!TARGET_PREFIXED) - rc = force_const_mem (<MODE>mode, rc); - - operands[3] = rc; -} - [(set_attr "type" "veclogical,integer") - (set_attr "length" "16")]) - -;; 16-bit floating point absolute value - -(define_insn_and_split "abs<mode>2" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr") - (abs:FP16 - (match_operand:FP16 1 "gpc_reg_operand" "wa,wr"))) - (clobber (match_scratch:FP16 2 "=&wa,&r"))] - "" - "#" - "&& 1" - [(set (match_dup 2) - (match_dup 3)) - (set (match_dup 0) - (and:FP16 (match_dup 1) - (not:FP16 (match_dup 2))))] -{ - if (GET_CODE (operands[2]) == SCRATCH) - operands[2] = gen_reg_rtx (<MODE>mode); - - REAL_VALUE_TYPE dconst; - - gcc_assert (real_from_string (&dconst, "-0.0") == 0); - - rtx rc = const_double_from_real_value (dconst, <MODE>mode); - - if (!TARGET_PREFIXED) - rc = force_const_mem (<MODE>mode, rc); - - operands[3] = rc; -} - [(set_attr "type" "veclogical,integer") - (set_attr "length" "16")]) - -;; 16-bit negative floating point absolute value - -(define_insn_and_split "*nabs<mode>2" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr") - (neg:FP16 - (abs:FP16 - (match_operand:FP16 1 "gpc_reg_operand" "wa,wr")))) - (clobber (match_scratch:FP16 2 "=&wa,&r"))] - "" - "#" - "&& 1" - [(set (match_dup 2) - (match_dup 3)) - (set (match_dup 0) - (ior:FP16 (match_dup 1) - (match_dup 2)))] -{ - if (GET_CODE (operands[2]) == SCRATCH) - operands[2] = gen_reg_rtx (<MODE>mode); - - REAL_VALUE_TYPE dconst; - - gcc_assert (real_from_string (&dconst, "-0.0") == 0); - rtx rc = const_double_from_real_value (dconst, <MODE>mode); - - if (!TARGET_PREFIXED) - rc = force_const_mem (<MODE>mode, rc); - - operands[3] = rc; -} - [(set_attr "type" "veclogical,integer") - (set_attr "length" "16")]) - -;; Add logical operations for 16-bit floating point types that are used -;; for things like negate, abs, and negative abs. Possibly in the -;; future we might need logical operators for extracting exponents and -;; mantissas. -(define_expand "and<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (and:FP16 (match_operand:FP16 1 "gpc_reg_operand") - (match_operand:FP16 2 "gpc_reg_operand")))] - "" - "") - -(define_expand "ior<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (ior:FP16 (match_operand:FP16 1 "gpc_reg_operand") - (match_operand:FP16 2 "gpc_reg_operand")))] - "" - "") - -(define_expand "xor<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (xor:FP16 (match_operand:FP16 1 "gpc_reg_operand") - (match_operand:FP16 2 "gpc_reg_operand")))] - "" - "") - -(define_expand "nor<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (and:FP16 - (not:FP16 (match_operand:FP16 1 "gpc_reg_operand")) - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand"))))] - "" - "") - -(define_expand "andn<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (and:FP16 - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand")) - (match_operand:FP16 1 "gpc_reg_operand")))] - "" - "") - -(define_expand "eqv<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (not:FP16 - (xor:FP16 (match_operand:FP16 1 "gpc_reg_operand") - (match_operand:FP16 2 "gpc_reg_operand"))))] - "" - "") - -;; Rewrite nand into canonical form -(define_expand "nand<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (ior:FP16 - (not:FP16 (match_operand:FP16 1 "gpc_reg_operand")) - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand"))))] - "" - "") - -;; The canonical form is to have the negated element first, so we need to -;; reverse arguments. -(define_expand "iorn<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (ior:FP16 - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand")) - (match_operand:FP16 1 "gpc_reg_operand")))] - "" - "") - -;; AND, IOR, and XOR insns. Unlike HImode operations prefer using -;; floating point/vector registers over GPRs. -(define_insn "*bool<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,r") - (match_operator:FP16 3 "boolean_operator" - [(match_operand:FP16 1 "gpc_reg_operand" "wa,r") - (match_operand:FP16 2 "gpc_reg_operand" "wa,r")]))] - "" - "@ - xxl%q3 %x0,%x1,%x2 - %q3 %0,%1,%2" - [(set_attr "type" "veclogical,logical")]) - -;; ANDC, IORC, and EQV insns. -(define_insn "*boolc<mode>3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=wa,r") - (match_operator:GPR 3 "boolean_operator" - [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "wa,r")) - (match_operand:GPR 1 "gpc_reg_operand" "wa,r")]))] - "" - "@ - xxl%q3 %x0,%x1,%x0 - %q3 %0,%1,%2" - [(set_attr "type" "veclogical,logical")]) - -;; NOR and NAND insns. -(define_insn "*boolcc<mode>3" - [(set (match_operand:GPR 0 "gpc_reg_operand" "=wa,r") - (match_operator:GPR 3 "boolean_operator" - [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "wa,r")) - (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "wa,r"))]))] - "" - "@ - xxl%q3 %x0,%x1,%x2 - %q3 %0,%1,%2" - [(set_attr "type" "veclogical,logical")]) - -;; Add vectorization support for 16-bit floating point. - -;; Binary operators being vectorized. -(define_insn_and_split "<fp16_names><mode>3" - [(set (match_operand:VFP16_HW 0 "vsx_register_operand") - (FP16_BINARY_OP:VFP16_HW - (match_operand:VFP16_HW 1 "vsx_register_operand") - (match_operand:VFP16_HW 2 "vsx_register_operand")))] - "can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - fp16_vectorization (<CODE>, operands[0], operands[1], operands[2], NULL_RTX, - FP16_BINARY); - DONE; -}) - -;; FMA operations being vectorized. -(define_insn_and_split "fma<mode>4" - [(set (match_operand:VFP16_HW 0 "vsx_register_operand") - (fma:VFP16_HW - (match_operand:VFP16_HW 1 "vsx_register_operand") - (match_operand:VFP16_HW 2 "vsx_register_operand") - (match_operand:VFP16_HW 3 "vsx_register_operand")))] - "can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - fp16_vectorization (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_FMA); - DONE; -}) - -(define_insn_and_split "*fms<mode>4" - [(set (match_operand:VFP16_HW 0 "vsx_register_operand") - (fma:VFP16_HW - (match_operand:VFP16_HW 1 "vsx_register_operand") - (match_operand:VFP16_HW 2 "vsx_register_operand") - (neg:VFP16_HW - (match_operand:VFP16_HW 3 "vsx_register_operand"))))] - "can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - fp16_vectorization (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_FMS); - DONE; -}) - -(define_insn_and_split "*nfma<mode>4" - [(set (match_operand:VFP16_HW 0 "vsx_register_operand") - (neg:VFP16_HW - (fma:VFP16_HW - (match_operand:VFP16_HW 1 "vsx_register_operand") - (match_operand:VFP16_HW 2 "vsx_register_operand") - (match_operand:VFP16_HW 3 "vsx_register_operand"))))] - "can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - fp16_vectorization (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMA); - DONE; -}) - -(define_insn_and_split "*nfms<mode>4" - [(set (match_operand:VFP16_HW 0 "vsx_register_operand") - (neg:VFP16_HW - (fma:VFP16_HW - (match_operand:VFP16_HW 1 "vsx_register_operand") - (match_operand:VFP16_HW 2 "vsx_register_operand") - (neg:VFP16_HW - (match_operand:VFP16_HW 3 "vsx_register_operand")))))] - "can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - fp16_vectorization (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMS); - DONE; -}) - -;; Vector Pack support. - -(define_expand "vec_pack_trunc_v4sf_v8hf" - [(match_operand:V8HF 0 "vfloat_operand") - (match_operand:V4SF 1 "vfloat_operand") - (match_operand:V4SF 2 "vfloat_operand")] - "TARGET_FLOAT16_HW" -{ - rtx r1 = gen_reg_rtx (V8HFmode); - rtx r2 = gen_reg_rtx (V8HFmode); - - emit_insn (gen_xvcvsphp_v8hf (r1, operands[1])); - emit_insn (gen_xvcvsphp_v8hf (r2, operands[2])); - rs6000_expand_extract_even (operands[0], r1, r2); - DONE; -}) - -(define_expand "vec_pack_trunc_v4sf_v8bf" - [(match_operand:V8BF 0 "vfloat_operand") - (match_operand:V4SF 1 "vfloat_operand") - (match_operand:V4SF 2 "vfloat_operand")] - "TARGET_BFLOAT16_HW" -{ - rtx r1 = gen_reg_rtx (V8BFmode); - rtx r2 = gen_reg_rtx (V8BFmode); - - emit_insn (gen_xvcvspbf16_v8bf (r1, operands[1])); - emit_insn (gen_xvcvspbf16_v8bf (r2, operands[2])); - rs6000_expand_extract_even (operands[0], r1, r2); - DONE; -}) - -;; Used for vector conversion to _Float16 -(define_insn "xvcvsphp_v8hf" - [(set (match_operand:V8HF 0 "vsx_register_operand" "=wa") - (unspec:V8HF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_XVCVSPHP_V8HF))] - "TARGET_FLOAT16_HW" - "xvcvsphp %x0,%x1" -[(set_attr "type" "vecfloat")]) - -;; Used for vector conversion to __bfloat16 -(define_insn "xvcvspbf16_v8bf" - [(set (match_operand:V8BF 0 "vsx_register_operand" "=wa") - (unspec:V8BF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_XVCVSPBF16_V8BF))] - "TARGET_BFLOAT16_HW" - "xvcvspbf16 %x0,%x1" - [(set_attr "type" "vecfloat")]) - -;; Vector unpack support. Given the name is for the type being -;; unpacked, we can unpack both __bfloat16 and _Float16. - -;; Unpack vector _Float16 -(define_expand "vec_unpacks_hi_v8hf" - [(match_operand:V4SF 0 "vfloat_operand") - (match_operand:V8HF 1 "vfloat_operand")] - "TARGET_FLOAT16_HW" -{ - rtx reg = gen_reg_rtx (V8HFmode); - - rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); - emit_insn (gen_xvcvhpsp_v8hf (operands[0], reg)); - DONE; -}) - -(define_expand "vec_unpacks_lo_v8hf" - [(match_operand:V4SF 0 "vfloat_operand") - (match_operand:V8HF 1 "vfloat_operand")] - "TARGET_FLOAT16_HW" -{ - rtx reg = gen_reg_rtx (V8HFmode); - - rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); - emit_insn (gen_xvcvhpsp_v8hf (operands[0], reg)); - DONE; -}) - -;; Used for vector conversion from _Float16 -(define_insn "xvcvhpsp_v8hf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:V8HF 1 "vsx_register_operand" "wa")] - UNSPEC_CVT_FP16_TO_V4SF))] - "TARGET_BFLOAT16_HW" - "xvcvhpsp %x0,%x1" - [(set_attr "type" "vecperm")]) - -;; Unpack vector __bfloat16 -(define_expand "vec_unpacks_hi_v8bf" - [(match_operand:V4SF 0 "vfloat_operand") - (match_operand:V8BF 1 "vfloat_operand")] - "TARGET_BFLOAT16_HW" -{ - rtx reg = gen_reg_rtx (V8BFmode); - - rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); - emit_insn (gen_xvcvbf16spn_v8bf (operands[0], reg)); - DONE; -}) - -(define_expand "vec_unpacks_lo_v8bf" - [(match_operand:V4SF 0 "vfloat_operand") - (match_operand:V8BF 1 "vfloat_operand")] - "TARGET_BFLOAT16_HW" -{ - rtx reg = gen_reg_rtx (V8BFmode); - - rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); - emit_insn (gen_xvcvbf16spn_v8bf (operands[0], reg)); - DONE; -}) - -;; Used for vector conversion from __bfloat16 -(define_insn "xvcvbf16spn_v8bf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:V8BF 1 "vsx_register_operand" "wa")] - UNSPEC_CVT_FP16_TO_V4SF))] - "TARGET_BFLOAT16_HW" - "xvcvbf16spn %x0,%x1" - [(set_attr "type" "vecperm")]) diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 6b17112ed0da..9bf971370d41 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -258,19 +258,6 @@ extern bool vec_const_128bit_to_bytes (rtx, machine_mode, extern unsigned constant_generates_lxvkq (vec_const_128bit_type *); extern unsigned constant_generates_xxspltiw (vec_const_128bit_type *); extern unsigned constant_generates_xxspltidp (vec_const_128bit_type *); - -/* From float16.cc. */ -/* Optimize bfloat16 and float16 operations. */ -enum fp16_operation { - FP16_BINARY, /* Bfloat16/float16 binary op. */ - FP16_FMA, /* (a * b) + c. */ - FP16_FMS, /* (a * b) - c. */ - FP16_NFMA, /* - ((a * b) + c). */ - FP16_NFMS /* - ((a * b) - c). */ -}; - -extern void fp16_vectorization (enum rtx_code, rtx, rtx, rtx, rtx, - enum fp16_operation); #endif /* RTX_CODE */ #ifdef TREE_CODE diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 7850affe6afc..0249219bbbc9 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -343,21 +343,11 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); || ((MODE) == TDmode) \ || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))) -/* Do we have conversion support in hardware for the 16-bit floating point? */ -#define TARGET_BFLOAT16_HW (TARGET_BFLOAT16 && TARGET_POWER10) -#define TARGET_FLOAT16_HW (TARGET_FLOAT16 && TARGET_POWER9) - /* Is this a valid 16-bit scalar floating point mode? */ #define FP16_SCALAR_MODE_P(MODE) \ (((MODE) == HFmode && TARGET_FLOAT16) \ || ((MODE) == BFmode && TARGET_BFLOAT16)) -/* Is this a valid 16-bit scalar floating point mode that has hardware - conversions? */ -#define FP16_HW_SCALAR_MODE_P(MODE) \ - (((MODE) == HFmode && TARGET_FLOAT16_HW) \ - || ((MODE) == BFmode && TARGET_BFLOAT16_HW)) - /* Is this a valid 16-bit vector floating point mode? */ #define FP16_VECTOR_MODE_P(MODE) \ (((MODE) == V8HFmode && TARGET_FLOAT16) \ diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000 index c8f19865311c..a5d1c27424f3 100644 --- a/gcc/config/rs6000/t-rs6000 +++ b/gcc/config/rs6000/t-rs6000 @@ -87,10 +87,6 @@ rs6000-c.o: $(srcdir)/config/rs6000/rs6000-c.cc rs6000-builtins.h $(COMPILE) $< $(POSTCOMPILE) -float16.o: $(srcdir)/config/rs6000/float16.cc - $(COMPILE) $< - $(POSTCOMPILE) - #$(srcdir)/config/rs6000/fusion.md: $(srcdir)/config/rs6000/genfusion.pl # $(srcdir)/config/rs6000/genfusion.pl > $(srcdir)/config/rs6000/fusion.md diff --git a/libgcc/config.host b/libgcc/config.host index ea5853d34b79..82ea1772f516 100644 --- a/libgcc/config.host +++ b/libgcc/config.host @@ -1302,18 +1302,6 @@ powerpc*-*-linux*) tmake_file="${tmake_file} rs6000/t-float128-p10-hw" fi - if test $libgcc_cv_powerpc_float16 = yes; then - tmake_file="${tmake_file} rs6000/t-float16" - fi - - if test $libgcc_cv_powerpc_bfloat16 = yes; then - tmake_file="${tmake_file} rs6000/t-bfloat16" - - if test $libgcc_cv_powerpc_bfloat16 = yes; then - tmake_file="${tmake_file} rs6000/t-both-fp16" - fi - fi - extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o" md_unwind_header=rs6000/linux-unwind.h ;; diff --git a/libgcc/config/rs6000/sfp-machine.h b/libgcc/config/rs6000/sfp-machine.h index 642d2fc4f215..f0ede0e042a3 100644 --- a/libgcc/config/rs6000/sfp-machine.h +++ b/libgcc/config/rs6000/sfp-machine.h @@ -22,9 +22,6 @@ typedef unsigned int UTItype __attribute__ ((mode (TI))); #define _FP_I_TYPE int #endif /* 32-bits */ -#define _FP_NANFRAC_H _FP_QNANBIT_H -#define _FP_NANFRAC_B _FP_QNANBIT_B - /* The type of the result of a floating point comparison. This must match `__libgcc_cmp_return__' in GCC for the target. */ typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__))); @@ -65,8 +62,6 @@ typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__))); #define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1 #endif -#define _FP_NANSIGN_H 1 -#define _FP_NANSIGN_B 1 #define _FP_NANSIGN_S 0 #define _FP_NANSIGN_D 0 #define _FP_NANSIGN_Q 0 @@ -166,48 +161,3 @@ void __sfp_handle_exceptions (int); # define strong_alias(name, aliasname) _strong_alias(name, aliasname) # define _strong_alias(name, aliasname) \ extern __typeof (name) aliasname __attribute__ ((alias (#name))); - -/* Add prototypes for the HFmode and BFmode functions. */ -typedef double DFtype2; -typedef float SFtype2; -typedef int DItype2 __attribute__ ((mode (DI))); -typedef unsigned int UDItype2 __attribute__ ((mode (DI))); -typedef int SItype2 __attribute__ ((mode (SI))); -typedef unsigned int USItype2 __attribute__ ((mode (SI))); - -#ifdef __FLOAT16__ -typedef float HFtype2 __attribute__ ((mode (HF))); - -extern CMPtype __eqhf2 (HFtype2, HFtype2); -extern DFtype2 __extendhfdf2 (HFtype2); -extern SFtype2 __extendhfsf2 (HFtype2); -extern DItype2 __fixhfdi (HFtype2); -extern SItype2 __fixhfsi (HFtype2); -extern UDItype2 __fixunshfdi (HFtype2); -extern USItype2 __fixunshfsi (HFtype2); -extern HFtype2 __floatdihf (DItype2); -extern HFtype2 __floatsihf (SItype2); -extern HFtype2 __floatundihf (UDItype2); -extern HFtype2 __floatunsihf (USItype2); -extern HFtype2 __truncdfhf2 (DFtype2); -extern HFtype2 __truncsfhf2 (SFtype2); -#endif - -#ifdef __BFLOAT16__ -typedef float BFtype2 __attribute__ ((mode (BF))); - -extern SFtype2 __extendbfsf2 (BFtype2); -extern BFtype2 __floatdibf (DItype2); -extern BFtype2 __floatsibf (SItype2); -extern BFtype2 __floatundibf (UDItype2); -extern BFtype2 __floatunsibf (USItype2); -extern BFtype2 __truncdfbf2 (DFtype2); -extern BFtype2 __truncsfbf2 (SFtype2); -#endif - -#if defined(__FLOAT16__) && defined(__BFLOAT16__) -extern HFtype2 __truncbfhf2 (BFtype2); -extern BFtype2 __trunchfbf2 (HFtype2); -#endif - - diff --git a/libgcc/config/rs6000/t-bfloat16 b/libgcc/config/rs6000/t-bfloat16 deleted file mode 100644 index cade2439c780..000000000000 --- a/libgcc/config/rs6000/t-bfloat16 +++ /dev/null @@ -1,30 +0,0 @@ -# __bfloat16 library support - -bfp16_funcs = extendbfsf2 floatdibf floatsibf floatundibf floatunsibf \ - truncdfbf2 truncsfbf2 - -bfp16_src = $(addprefix $(srcdir)/soft-fp/,$(addsuffix .c,$(bfp16_funcs))) -bfp16_obj = $(addsuffix $(objext),$(bfp16_funcs)) - -BFP16_CFLAGS = -mbfloat16 -Wno-psabi \ - -I$(srcdir)/soft-fp \ - -I$(srcdir)/config/rs6000 \ - -$(bfp16_obj) : INTERNAL_CFLAGS += $(BFP16_CFLAGS) - -# For now, only put it in the static library -# LIB2ADD += $(bfp16_src) - -LIB2ADD_ST += $(bfp16_src) - -.PHONY: test-bfloat16 clean-bfloat16 - -test-bfloat16: - @echo "bfp16_src:"; \ - for x in $(bfp16_src); do echo " $$x"; done; \ - echo; \ - echo "bfp16_obj:"; \ - for x in $(bfp16_obj); do echo " $$x"; done; - -clean-bfloat16: - @$(MULTICLEAN) multi-clean DO=clean-float16 diff --git a/libgcc/config/rs6000/t-both-fp16 b/libgcc/config/rs6000/t-both-fp16 deleted file mode 100644 index d51b7abbf086..000000000000 --- a/libgcc/config/rs6000/t-both-fp16 +++ /dev/null @@ -1,28 +0,0 @@ -# Conversion between __bfloat16 and _Float16 - -both_fp16_funcs = truncbfhf2 trunchfbf2 -both_fp16_src = $(addprefix $(srcdir)/soft-fp/,$(addsuffix .c,$(both_fp16_funcs))) -both_fp16_obj = $(addsuffix $(objext),$(both_fp16_funcs)) - -BOTH_FP16_CFLAGS = -mfloat16 -mbfloat16 -Wno-psabi \ - -I$(srcdir)/soft-fp \ - -I$(srcdir)/config/rs6000 \ - -$(both_fp16_obj) : INTERNAL_CFLAGS += $(BOTH_FP16_CFLAGS) - -# For now, only put it in the static library -# LIB2ADD += $(both_fp16_src) - -LIB2ADD_ST += $(both_fp16_src) - -.PHONY: test-both-fp16 clean-both-fp16 - -test-both-fp16: - @echo "both_fp16_src:"; \ - for x in $(both_fp16_src); do echo " $$x"; done; \ - echo; \ - echo "both_fp16_obj:"; \ - for x in $(both_fp16_obj); do echo " $$x"; done; - -clean-both-fp16: - @$(MULTICLEAN) multi-clean DO=clean-both-fp16 diff --git a/libgcc/config/rs6000/t-float16 b/libgcc/config/rs6000/t-float16 deleted file mode 100644 index f961097e85d1..000000000000 --- a/libgcc/config/rs6000/t-float16 +++ /dev/null @@ -1,31 +0,0 @@ -# _Float16 library support - -fp16_funcs = eqhf2 extendhfdf2 extendhfsf2 \ - fixhfdi fixhfsi fixunshfdi fixunshfsi \ - floatdihf floatsihf floatundihf floatunsihf \ - truncdfhf2 truncsfhf2 - -fp16_src = $(addprefix $(srcdir)/soft-fp/,$(addsuffix .c,$(fp16_funcs))) -fp16_obj = $(addsuffix $(objext),$(fp16_funcs)) - -FP16_CFLAGS = -mfloat16 -Wno-psabi \ - -I$(srcdir)/soft-fp -I$(srcdir)/config/rs6000 - -$(fp16_obj) : INTERNAL_CFLAGS += $(FP16_CFLAGS) - -# For now, only put it in the static library -# LIB2ADD += $(fp16_src) - -LIB2ADD_ST += $(fp16_src) - -.PHONY: test-float16 clean-float16 - -test-float16: - @echo "fp16_src:"; \ - for x in $(fp16_src); do echo " $$x"; done; \ - echo; \ - echo "fp16_obj:"; \ - for x in $(fp16_obj); do echo " $$x"; done; - -clean-float16: - @$(MULTICLEAN) multi-clean DO=clean-float16 diff --git a/libgcc/configure b/libgcc/configure index ed7ea9e7d621..d5e80d227ff6 100755 --- a/libgcc/configure +++ b/libgcc/configure @@ -5188,8 +5188,6 @@ case ${host} in # check if we have VSX (ISA 2.06) support to build the software libraries, and # whether the assembler can handle xsaddqp for hardware support. Also check if # a new glibc is being used so that __builtin_cpu_supports can be used. -# -# Add float16 support also powerpc*-*-linux*) saved_CFLAGS="$CFLAGS" CFLAGS="$CFLAGS -mabi=altivec -mvsx -mfloat128" @@ -5284,48 +5282,6 @@ fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_powerpc_3_1_float128_hw" >&5 $as_echo "$libgcc_cv_powerpc_3_1_float128_hw" >&6; } CFLAGS="$saved_CFLAGS" - - CFLAGS="$CFLAGS -mfloat16 -Wno-psabi" - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the PowerPC can build the _Float16 libraries" >&5 -$as_echo_n "checking whether the PowerPC can build the _Float16 libraries... " >&6; } -if ${libgcc_cv_powerpc_float16+:} false; then : - $as_echo_n "(cached) " >&6 -else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -/* end confdefs.h. */ -_Float16 addf16 (_Float16 a, _Float16 b) { return a + b; } -_ACEOF -if ac_fn_c_try_compile "$LINENO"; then : - libgcc_cv_powerpc_float16=yes -else - libgcc_cv_powerpc_float16=no -fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext -fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_powerpc_float16" >&5 -$as_echo "$libgcc_cv_powerpc_float16" >&6; } - CFLAGS="$saved_CFLAGS" - - CFLAGS="$CFLAGS -mbfloat16 -Wno-psabi" - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the PowerPC can build __bfloat16 libraries" >&5 -$as_echo_n "checking whether the PowerPC can build __bfloat16 libraries... " >&6; } -if ${libgcc_cv_powerpc_bfloat16+:} false; then : - $as_echo_n "(cached) " >&6 -else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -/* end confdefs.h. */ -__bfloat16 addbf16 (__bfloat16 a, __bfloat16 b) { return a + b; } -_ACEOF -if ac_fn_c_try_compile "$LINENO"; then : - libgcc_cv_powerpc_bfloat16=yes -else - libgcc_cv_powerpc_bfloat16=no -fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext -fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_powerpc_bfloat16" >&5 -$as_echo "$libgcc_cv_powerpc_bfloat16" >&6; } - CFLAGS="$saved_CFLAGS" esac # Collect host-machine-specific information. diff --git a/libgcc/configure.ac b/libgcc/configure.ac index 464acdee14c3..65cd3c6aa1a5 100644 --- a/libgcc/configure.ac +++ b/libgcc/configure.ac @@ -407,8 +407,6 @@ case ${host} in # check if we have VSX (ISA 2.06) support to build the software libraries, and # whether the assembler can handle xsaddqp for hardware support. Also check if # a new glibc is being used so that __builtin_cpu_supports can be used. -# -# Add float16 support also powerpc*-*-linux*) saved_CFLAGS="$CFLAGS" CFLAGS="$CFLAGS -mabi=altivec -mvsx -mfloat128" @@ -467,24 +465,6 @@ powerpc*-*-linux*) [libgcc_cv_powerpc_3_1_float128_hw=yes], [libgcc_cv_powerpc_3_1_float128_hw=no])]) CFLAGS="$saved_CFLAGS" - - CFLAGS="$CFLAGS -mfloat16 -Wno-psabi" - AC_CACHE_CHECK([whether the PowerPC can build the _Float16 libraries], - [libgcc_cv_powerpc_float16], - [AC_COMPILE_IFELSE( - [AC_LANG_SOURCE([_Float16 addf16 (_Float16 a, _Float16 b) { return a + b; }])], - [libgcc_cv_powerpc_float16=yes], - [libgcc_cv_powerpc_float16=no])]) - CFLAGS="$saved_CFLAGS" - - CFLAGS="$CFLAGS -mbfloat16 -Wno-psabi" - AC_CACHE_CHECK([whether the PowerPC can build __bfloat16 libraries], - [libgcc_cv_powerpc_bfloat16], - [AC_COMPILE_IFELSE( - [AC_LANG_SOURCE([__bfloat16 addbf16 (__bfloat16 a, __bfloat16 b) { return a + b; }])], - [libgcc_cv_powerpc_bfloat16=yes], - [libgcc_cv_powerpc_bfloat16=no])]) - CFLAGS="$saved_CFLAGS" esac # Collect host-machine-specific information.
