https://gcc.gnu.org/g:b250a3f74d75eb0461f815559d8aa90f5b3f3fbf
commit b250a3f74d75eb0461f815559d8aa90f5b3f3fbf Author: Michael Meissner <[email protected]> Date: Fri Oct 31 18:24:17 2025 -0400 Add --with-powerpc-16bit-floating-point. 2025-10-31 Michael Meissner <[email protected]> gcc/ * config.gcc (powerpc*-*-*): Add support for the configuration option --with-powerpc-16bit-floating-point. * config/rs6000/rs6000-cpus.def (TARGET_16BIT_FLOATING_POINT): Likewise. (ISA_2_7_MASKS_SERVER): Likewise. (POWERPC_MASKS): Likewise. Diff: --- gcc/config.gcc | 9 +++++++++ gcc/config/rs6000/rs6000-cpus.def | 31 ++++++++++++++----------------- 2 files changed, 23 insertions(+), 17 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index d6d4d06c3107..7a0cd0122cd2 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -5799,6 +5799,15 @@ case "${target}" in elif test x$with_long_double_format = xibm; then tm_defines="${tm_defines} TARGET_IEEEQUAD_DEFAULT=0" fi + + # Test if we should enable 16-bit floating point on the platforms + # where we can support __bfloat16 and _Float16. + if test x$with_powerpc_16bit_floating_point = xyes; then + tm_defines="${tm_defines} POWERPC_16BIT_FLOATING_POINT_DEFAULT=1" + + elif test x$with_powerpc_16bit_floating_point = xyes; then + tm_defines="${tm_defines} POWERPC_16BIT_FLOATING_POINT_DEFAULT=0" + fi ;; s390*-*-*) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 9e6a0b801523..a5ab7fe7317f 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -85,24 +85,26 @@ | OPTION_MASK_ALTIVEC \ | OPTION_MASK_VSX) +/* Determine whether to enable 16-bit floating point types on power8 systems + and above. */ +#if POWERPC_16BIT_FLOATING_POINT_DEFAULT +#define TARGET_16BIT_FLOATING_POINT (OPTION_MASK_BFLOAT16 \ + | OPTION_MASK_FLOAT16) + +#else +#define TARGET_16BIT_FLOATING_POINT 0 +#endif + /* For now, don't provide an embedded version of ISA 2.07. Do not set power8 fusion here, instead set it in rs6000.cc if we are tuning for a power8 system. */ - -/* In the future consider adding OPTION_MASK_BFLOAT16 and OPTION_MASK_FLOAT16 - when the 16-bit floating support is less experimental. ISA 2.7 (power8) is - the minimum ISA that can support 16-bit point floating point because we need - direct move to load 16-bit values into floating point/vector registers from - GPRs. ISA 3.0 (power9) adds the ability to load/store 16-bit values - directly to floating point/vector registers, and hardware instructions to - convert between _Float16 and float. ISA 3.1 (power10) adds instructions to - convert between __bfloat16 and float vector types. */ #define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \ | OPTION_MASK_P8_VECTOR \ | OPTION_MASK_CRYPTO \ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_QUAD_MEMORY \ - | OPTION_MASK_QUAD_MEMORY_ATOMIC) + | OPTION_MASK_QUAD_MEMORY_ATOMIC \ + | TARGET_16BIT_FLOATING_POINT) /* ISA masks setting fusion options. */ #define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \ @@ -161,12 +163,8 @@ #endif /* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */ - -/* In the future if 16-bit floating point is enabled by default for ISA 2.7 - (power8), add OPTION_MASK_FLOAT16 and OPTION_MASK_BFLOAT16 to - POWERPC_MASKS. */ #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ - /* | OPTION_MASK_BFLOAT16 */ \ + | OPTION_MASK_BFLOAT16 \ | OPTION_MASK_CMPB \ | OPTION_MASK_CRYPTO \ | OPTION_MASK_DFP \ @@ -174,11 +172,10 @@ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_FLOAT128_KEYWORD \ - /* | OPTION_MASK_FLOAT16 */ \ + | OPTION_MASK_FLOAT16 \ | OPTION_MASK_FPRND \ | OPTION_MASK_P10_FUSION \ | OPTION_MASK_HTM \ - | OPTION_MASK_FLOAT16 \ | OPTION_MASK_ISEL \ | OPTION_MASK_MFCRF \ | OPTION_MASK_MMA \
