https://gcc.gnu.org/g:0e71df96e2e34d1d6163bdeab06edecb34fb1c16
commit r16-4917-g0e71df96e2e34d1d6163bdeab06edecb34fb1c16 Author: Takayuki 'January June' Suwa <[email protected]> Date: Fri Oct 31 15:22:35 2025 +0900 xtensa: Make use of ROUND.S instruction Due to inconsistencies in the behavior of rounding half, making this machine instruction available was retracted in a previous commit (5f3b5b0616fe883e86e95d9476371cf87059ca7f), but it may be useful to have it available if strict implementation of floating-point arithmetic is not required. gcc/ChangeLog: * config/xtensa/xtensa.md (c_enum "unspec", int_iterator ANY_ROUND): Add UNSPEC_ROUND. (int_attr m_round): Add a pair of UNSPEC_ROUND and "round". (int_attr c_round): New integer iterator attribute, that expands to "flag_unsafe_math_optimizations" in the case of UNSPEC_ROUND, and to "1" otherwise. (l<m_round>sfsi2, *l<m_round>sfsi2_2x, *l<m_round>sfsi2_scaled): Append " && <c_round>" to the conditions. Diff: --- gcc/config/xtensa/xtensa.md | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index e05b35bb964b..7dc941f95714 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -43,6 +43,7 @@ UNSPEC_FRAME_BLOCKAGE UNSPEC_CEIL UNSPEC_FLOOR + UNSPEC_ROUND ]) (define_c_enum "unspecv" [ @@ -104,8 +105,11 @@ ;; This iterator and attribute allow FP-to-integer rounding of two types ;; to be generated from one template. -(define_int_iterator ANY_ROUND [UNSPEC_CEIL UNSPEC_FLOOR]) -(define_int_attr m_round [(UNSPEC_CEIL "ceil") (UNSPEC_FLOOR "floor")]) +(define_int_iterator ANY_ROUND [UNSPEC_CEIL UNSPEC_FLOOR UNSPEC_ROUND]) +(define_int_attr m_round [(UNSPEC_CEIL "ceil") (UNSPEC_FLOOR "floor") + (UNSPEC_ROUND "round")]) +(define_int_attr c_round [(UNSPEC_CEIL "1") (UNSPEC_FLOOR "1") + (UNSPEC_ROUND "flag_unsafe_math_optimizations")]) ;; Attributes. @@ -1168,7 +1172,7 @@ (define_insn "l<m_round>sfsi2" [(set (match_operand:SI 0 "register_operand" "=a") (unspec:SI [(match_operand:SF 1 "register_operand" "f")] ANY_ROUND))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && <c_round>" "<m_round>.s\t%0, %1, 0" [(set_attr "type" "fconv") (set_attr "mode" "SF") @@ -1178,7 +1182,7 @@ [(set (match_operand:SI 0 "register_operand" "=a") (unspec:SI [(plus:SF (match_operand:SF 1 "register_operand" "f") (match_dup 1))] ANY_ROUND))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && <c_round>" "<m_round>.s\t%0, %1, 1" [(set_attr "type" "fconv") (set_attr "mode" "SF") @@ -1188,7 +1192,7 @@ [(set (match_operand:SI 0 "register_operand" "=a") (unspec:SI [(mult:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "fix_scaling_operand" ""))] ANY_ROUND))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && <c_round>" "<m_round>.s\t%0, %1, %U2" [(set_attr "type" "fconv") (set_attr "mode" "SF")
