The branch 'riscv/heads/gcc-15-with-riscv-opts' was updated to point to:
cd6efdbdcbab... RISC-V: Combine vec_duplicate + vwaddu.wv to vwaddu.wx on G
It previously pointed to:
ff10a76379f4... RISC-V: Combine vec_duplicate + vwaddu.wv to vwaddu.wx on G
Diff:
!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
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ff10a76... RISC-V: Combine vec_duplicate + vwaddu.wv to vwaddu.wx on G
867c76e... ISC-V: Add test for vec_duplicate + vwaddu.wv signed combin
249d80f... Fixup merge conflict
3164c5b... [PATCH v2] RISC-V: Fix type of CFA during stack probe [PR12
1bb8c89... [RISC-V][PR target/122147] Avoid creating (subreg (mem)) in
496c7a5... [PR target/118945][PATCH v3] RISC-V: Add 'prefer_agnostic'
d644cc4... [RISC-V][PR rtl-optimization/121937] Don't call neg_poly_in
6f8475e... [PATCH v2] RISC-V: fix __builtin_round NaN handling [PR tar
3f7572a... [RISC-V][PR target/122051] Fix pmode_reg_or_uimm5_operand f
9d127d4... [RISC-V][PR target/122106] Add missing predicate on crc exp
6361cff... [PATCH][PR target/121778] RISC-V: Improve rotation detectio
6c35a54... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
e4ec87a... RISC-V: Add missing define_insn_reservation to tt-ascalon-d
772ec4d... [RISC-V][PR target/121983] Fix unprotected REGNO invocation
ac481eb... RISC-V: Improve slide patterns recognition
e093517... RISC-V: Only Save/Restore required registers for ILP32E/LP6
a462168... [RISC-V] Optimize clear-lowest-set-bit sequence when ctz is
0fb8269... RISC-V: Correct lmul estimation
8f51044... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
d391c19... [PR tree-optimization/58727] Don't over-simplify constants`
d9799b7... RISC-V: Add test for vec_duplicate + vwmulu.vv signed combi
ed33bb7... RISC-V: Add test for vec_duplicate + vwsubu.vv signed combi
9f2e8d7... RISC-V: Add test for vec_duplicate + vwaddu.vv signed combi
5ce29de... RISC-V: Combine vec_duplicate + vwaddu.vv to vwaddu.vx on G
45c4950... RISC-V: Allow profiles input in '--with-arch' option.
dc6066d... RISC-V: Configure Profiles definitions in the definition fi
a9fa032... RISC-V: Imply zicsr for sdtrig and ssstrict extensions.
ac187b4... Widening-Mul: Refine build_and_insert_cast when rhs is cast
dc3a35d... RISC-V: Fix vendor intrinsic tests for disabled multilib co
b711ad1... RISC-V: Support vnclip idiom testcase [PR120378]
be2fa61... Match: Support SAT_TRUNC variant NARROW_CLIP
c718eba... [RISC-V] Adjust ABI specification in recently added Andes t
e911256... RISC-V: Suppress cross CC sibcall optimization from vector
a799d7e... RISC-V: Add min/max patterns for ifcvt.
437086c... ifcvt: Clarify if_info.original_cost.
471cbcf... RISC-V: Fix can_find_related_mode_p for VLS types
f7fc258... RISC-V: Fix typo in tt-ascalon-d8's pipeline description [P
8aa4b28... RISC-V: Add pattern for vector-scalar single widening float
1bc0d7e... RISC-V: Add pattern for vector-scalar dual widening floatin
3b33628... RISC-V: Add pattern for vector-scalar single widening float
439ed14... RISC-V: Add pattern for vector-scalar widening floating-poi
6df8725... RISC-V: Adjust tt-ascalon-d8 branch cost
15a8b61... RISC-V: Add pattern for vector-scalar single-width floating
584fefa... RISC-V: Add pattern for vector-scalar single-width floating
446b49a... RISC-V: Add pattern for vector-scalar single-width floating
aecb3e4... RISC-V: Add pattern for vector-scalar widening floating-poi
c61162e... RISC-V: Add patterns for vector-scalar IEEE floating-point
51e7946... gcc: introduce the dep_fusion pass
2cae941... RISC-V: Add support for the XAndesvdot ISA extension.
c7c8a1c... [RISC-V] Fix ordering of pipeline models
9618ebc... RISC-V: Add support for the XAndesvpackfph ISA extension.
7024d02... RISC-V: Add test for vec_duplicate + vnmsub.vv unsigned com
e4bdcb6... RISC-V: Add test for vec_duplicate + vnmsub.vv signed combi
2a45294... RISC-V: Combine vec_duplicate + vnmsub.vv to vnmsub.vx on G
26cb012... dep_fusion: Fix if target does not have macro fusion [PR121
51ea80c... gcc: introduce the dep_fusion pass
0fa07d5... RISC-V: Add support for the XAndesvsintload ISA extension.
d0f27c9... RISC-V: Add support for the XAndesvbfhcvt ISA extension.
1d0225d... RISC-V: Add tt-ascalon-d8 pipeline description
de155f1... [RISC-V] Adjust recently added test
d7f71b9... RISC-V: Combine vec_duplicate + vmadd.vv to vmadd.vx on GR2
e48d1c1... RISC-V: Allow errors to be suppressed when parsing architec
1212411... RISC-V: Adjust the vmacc.vx combine test cases
6b003c1... RISC-V: Add test for vec_duplicate + vmadd.vv unsigned comb
496a710... RISC-V: Add test for vec_duplicate + vmadd.vv signed combin
988cbe7... RISC-V: Fix extension subset check in riscv_can_inline_p
361499b... RISC-V: Add support for the XAndesbfhcvt ISA extension.
b9e9e15... RISC-V: Add support for the XAndesperf ISA extension.
dbf2889... RISC-V: Add basic XAndes vendor extension support.
f641c4e... RISC-V: Add pattern for vector-scalar floating-point max
67dbe01... [RISC-V][PR target/121213] Avoid unnecessary sign extension
fdebd31... RISC-V: Fix is_vlmax_len_p and use for strided ops.
d0d31e8... RISC-V: Add Zbb extension sext testcase.
7795ac1... RISC-V: Update Zba 'shNadd.uw' testcase.`
d884306... RISC-V: Remove unused print_ext_doc_entry function [NFC]
2dedddc... [RISC-V] Improve initial RTL generation for SImode adds on
fa9c523... RISC-V: Add test case for unsigned scalar SAT_MUL form 4
4aa0de6... RISC-V: Add patterns for vector-scalar IEEE floating-point
8f93196... RISC-V: Add test for vec_duplicate + vnmsac.vv unsigned com
ac780e5... RISC-V: Add test for vec_duplicate + vnmsac.vv signed combi
ac70276... RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on G
95eae80... RISC-V: Add pattern for vector-scalar floating-point min
e8a6ad9... Remove xfail marker on RISC-V test
49f14af... RISC-V: testsuite: Fix vf_vfmul and vf_vfrdiv
e9e867c... More RISC-V testsuite hygiene
4f5bdd8... [committed] RISC-V Testsuite hygiene
772b431... [PATCH] RISC-V: Add pattern for reverse floating-point divi
1aaea6f... [PATCH] RISC-V: Add pattern for vector-scalar single-width
1f1819d... Fix RISC-V bootstrap
5db7105... RISC-V: Add test for vec_duplicate + vmacc.vv unsigned comb
5211e78... RISC-V: Add test for vec_duplicate + vmacc.vv signed combin
3c52fed... RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2
6fab0f7... RISC-V: Replace deprecated FUNCTION_VALUE/LIBCALL_VALUE mac
6df4b4a... Fix invalid right shift count with recent ifcvt changes
25c8c3f... [PR rtl-optimization/120553] Improve selecting between cons
f3ecc8f... RISC-V: Add testcase for scalar unsigned SAT_MUL form 3
730d65f... RISC-V: testsuite: Fix DejaGnu support for riscv_zvfh
4289250... [PR target/121213] Avoid unnecessary constant load in amosw
03f054b... regrename: treat writes as reads for fused instruction pair
84a65e1... ira: tie output allocnos for fused instruction pairs
7213d9e... [PATCH] RISC-V: Fix block matching in arch-canonicalize [PR
5c665ae... RISC-V: Update the comments of vx combine [NFC]
b8dd150... RISC-V: Add missed DONE for vx combine pattern [NFC]
2d4fd27... RISC-V: MIPS prefetch extensions for MIPS RV64 P8700 and ca
fa26ece... [PR target/119275][RISC-V] Avoid calling gen_lowpart in cas
437a2f8... [RISC-V][PR target/121531] Cover missing insn types in p400
c34fb13... [RISC-V][PR target/121160] Avoid bogus force_reg call
1052884... [RISC-V][PR target/121113] Handle HFmode in various insn re
3077c27... RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm com
bde7aad... RISC-V: Combine vec_duplicate + vmerge.vv to vmerge.vx on G
fd71e9c... RISC-V: Expand const_vector with 2 elts per pattern.
68d02f3... Improve initial code generation for addsi/adddi
892eb72... Don't run tests requiring "B" on designs without "B"
6e4f4c4... RISC-V: Add testcase for scalar unsigned SAT_MUL form 2
c6bbc3b... RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost
ddfc95f... RISC-V: Read extension data from riscv-ext*.def for arch-ca
eb234fe... RISC-V: Support -march=unset
f41f5a9... RISC-V: Fix scalar code-gen of unsigned SAT_MUL
f0d5653... RISC-V: Add testcases for signed avg ceil vx combine
96bd260... RISC-V: Adding H to the canonical order [PR121312]
b4f7554... RISC-V: Add testcases for unsigned avg ceil vx combine.
8d74998... RISC-V: Generate -mcpu and -mtune options from riscv-cores.
f32b334... RISC-V: Remove use of structured binding to fix compiler wa
dfd6241... RISC-V: Add test cases for mul based unsigned scalar SAT_MU
c2af6e2... RISC-V: Add test case for vaadd.vx combine polluting VXRM
459c892... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
361de94... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
a814033... RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2
c448775... RISC-V: Fix another vf FP16 combine run test failures
e76fe58... RISC-V: riscv-ext.def: Add allocated group IDs and group bi
32f1186... RISC-V: Prepare dynamic LMUL heuristic for SLP.
705d6ff... RISC-V: Remove user-level interrupts
6522e2f... RISC-V: Add support for resumable non-maskable interrupt (R
a4eb79b... riscv: testsuite: Fix misalignment check.
85ede0d... RISC-V: Add test case for vx combine polluting VXRM
f6c89b3... RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr
70fba49... RISC-V: Rework broadcast handling [PR121073].
73c7e4e... RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.
ab58123... Change bellow in comments to below
2526631... [RISC-V] Restrict generic-vector-ooo DFA
c219fca... [RISC-V] Add missing insn types to xiangshan.md and mips-p8
c206467... RISC-V: Add test for vec_duplicate + vaaddu.vv combine for
8df4a11... RISC-V: Allow VLS DImode for sat_op vx DImode pattern
4a8c136... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
db5e2b5... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
90b8e3f... RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on G
852382a... RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and
9c965eb... RISC-V: Refine the test case for vector avg_floor and avg_c
696b8df... RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg
57921bc... [PATCH] RISC-V: Vector-scalar widening negate-multiply-(sub
3a7139d... [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro
41b4e9a... RISC-V: Support RVVDImode for avg3_ceil auto vect
bdce872... RISC-V: Fix vsetvl merge rule.
c9a9e0b... RISC-V: Refine the scalar SAT_* test cases
97e0060... RISC-V: Support RVVDImode for avg3_floor auto vect
03ee905... [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.
8c7dfba... RISC-V: Add testcase for rv32 SAT_MUL from uint64
d20d8c9... [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtrac
c676770... RISC-V: Add testcases for unsigned vector SAT_SUB form 11 a
d996437... RISC-V: Make zero-stride load broadcast a tunable.
8029075... [RISC-V] Detect new fusions for RISC-V
272befd... RISCV: Remove the v extension requirement for sat scalar ru
e4b1e31... RISC-V: Add test for vec_duplicate + vssub.vv combine case
e24d788... RISC-V: Add test for vec_duplicate + vssub.vv combine case
70418e1... RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2
f99e834... [PATCH] RISC-V: Enable zvfh for vector-scalar half-float ru
9c448f3... [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB
cb3bb21... [RISC-V][PR target/120642] Avoid propagating constant AVL f
3b7f156... RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
5069c34... RISC-V: Do not use vsetivli for THeadVector.
9f6ef35... RISC-V: Ignore non-types in builtin function hash.
a589511... [committed][RISC-V] Fix testsuite fallout from check-functi
dcd6be5... RISC-V: Add test cases for unsigned scalar SAT_MUL from uin
bf98bc8... RISC-V: Implement unsigned scalar SAT_MUL from uint128_t
b4e210b... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
62b1ab1... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
8ce71c4... RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2
8578937... [RISC-V] Add basic instrumentation to fusion detection
c8b1211... RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2
41e6867... Refactor record_function_versions.
014cf5c... [RISC-V][PR target/118886] Refine when two insns are signal
9cd96ae... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
c49e6dc... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
18b9ffc... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
62ab97e... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
6b5d9bb... RISC-V: Reconcile the existing test due to cost model chang
7925715... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
82f59d7... RISC-V: Ignore -Oz for most rvv testcase [NFC]
7caa5ba... RISC-V: Primary vector pipeline model for sifive 7 series
dae6b21... RISC-V: Adding B ext, fp16 and missing scalar instruction t
a8109db... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
d5c0b98... RISC-V: Refactor the function bitmap_union_of_preds_with_en
b747001... RISC-V: Add pipeline-checker script
764765d... [RISC-V][PR target/119971] Avoid losing shift count masking
d0e0f72... RISC-V: update prepare_ternary_operands to handle vector-sc
ebcbac6... RISC-V: Fix build issue
8393fa2... RISC-V: Add comment and reorder the the include files in ri
11d9821... RISC-V: Add Profiles RVA/B23S64 support.
e5e953b... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
0e6b449... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
7f1849f... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
1b79fce... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
32c0f7b... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
bf7e430... RISC-V: Fix ICE for expand_select_vldi [PR120652]
e8bb1f6... [RISC-V] Force several tests to use rocket tuning
199aea6... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
6e1ce5a... RISC-V: Add test for vec_duplicate + vminu.vv combine case
4abc9d0... RISC-V: Add test for vec_duplicate + vminu.vv combine case
14e4268... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
7cd5aa1... RISC-V: Add generic tune as default.
89c1850... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
e1f983b... RISC-V: Adding cost model for zilsd
af22f68... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
5763383... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
bbd394d... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
47108b7... [PATCH v1] RISC-V: Use scratch reg for loop control
6978ac6... RISC-V: Add -fno-pie flags to testcases
ee470b5... RISC-V: Refine VX combine test case 0 to avoid code duplica
7a524c9... RISC-V: Update Profiles string in RV23.
b6eac14... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
c9a5f2b... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
db3258c... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
c3bfe3a... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
894c818... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
1f872bd... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
1b101a2... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
79b78c6... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
43de906... RISC-V: Prevent speculative vsetvl insn scheduling
f0b9a58... RISC-V: Add patterns for vector-scalar negate-(multiply-add
4d0a45b... RISC-V: testsuite: fix an obvious build error
c6f1e30... RISC-V: Regen riscv-ext.texi [NFC]
cc8b78a... RISC-V: Add test for vec_duplicate + vremu.vv combine case
c1865cd... RISC-V: Add test for vec_duplicate + vremu.vv combine case
abe3010... RISC-V: Reconcile the existing test for vremu.vx combine
cda9fc9... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
aea8e5a... [RISC-V] Enable more if-conversion on RISC-V
27eb198... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
d7b3620... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
b2d566d... RISC-V: Reconcile the existing test for vrem.vx combine
e8e0cc4... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
bad28fe... RISC-V: frm/mode-switch: robustify call_insn backtracking [
781dbef... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
b3860a2... RISC-V: frm/mode-switch: remove dubious frm edge insertion
2043b2a... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
a2ba577... [RISC-V] Handle 32bit operands in condition for conditional
928bb80... [to-be-committed][RISC-V] Handle 32bit operands in conditio
f15dbd6... RISC-V: Reconcile the existing test for vdivu.vx combine
2c37f73... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
9bd3e57... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
bf05926... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
493ff21... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
b06addf... [RISC-V] Improve signed division by 2^n
b788353... RISC-V: Don't use structured binding in riscv-common.cc
2cb6c81... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
19ada88... [RISC-V] Improve sequences to generate -1, 1 in some cases.
c558d17... RISC-V: Support Ssu64xl extension.
c21cfdd... RISC-V: Support Sstvecd extension.
ed69d9e... RISC-V: Support Sstvala extension.
f5369da... RISC-V: Support Sscounterenw extension.
babd6f0... RISC-V: Support Ssccptr extension.
532ec73... RISC-V: Support Smrnmi extension.
c88f20d... RISC-V: Support Sm/scsrind extensions.
11fec96... RISC-V: Update extension defination.
1b7f3c0... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
adf3925... [PATCH v2] RISC-V: Add svbare extension.
7914153... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
c881328... RISC-V: Add Shlcofideleg extension.
c5ad1ee... RISC-V: Reconcile the existing test for vdiv.vx combine
830cd4f... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
c8f98c3... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
131ded9... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
104ec3b... RISC-V: Use helper function to get FPR to VR move cost
d12616f... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
9a5250e... [PATCH] RISC-V: Add smcntrpmf extension.
9d95671... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
87759ca... RISC-V: Implement full-featured iterator for riscv_subset_l
ec76e0c... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
a57c75d... RISC-V: Fix line too long format issue for autovect.md [NFC
e0bab1e... RISC-V: Add test cases for avg_ceil vaadd implementation
257d3fb... RISC-V: Reconcile the existing test for avg_ceil
50331d9... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
f6633d1... RISC-V: Add minimal support of double trap extension 1.0
dd2b20b... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
cb19c72... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
87e2291... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
5ff39a6... RISC-V: Avoid division by zero in check_builtin_call [PR120
630bb2e... RISC-V: Add test cases for avg_floor vaadd implementation
5b84d31... RISC-V: Reconcile the existing test for avg_floor
1723e1e... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
1b9de35... [RISC-V] Add andi+bclr synthesis
e5a8d87... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
7792948... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
959cfe3... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
84472ea... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
c25a4a3... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
3860f7d... [RISC-V] shift+and+shift for logical and synthesis
32b10cf... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
f20ac87... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
fc3647f... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
3c2e0ef... RISC-V: Support CPUs in -march.
10350d2... RISC-V: Add autovec mode param.
b2c31a1... RISC-V: Default-initialize variable.
31805f3... RISC-V: Fix some dynamic LMUL costing.
50295e1... [RISC-V] Clear both upper and lower bits using 3 shifts
b5fb256... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
01a7d67... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
c04033b... [RISC-V] Clear high or low bits using shift pairs
4261924... [RISC-V] Improve (x << C1) + C2 split code
c2f046f... [RISC-V][PR target/120368] Fix 32bit shift on rv64
b108b7e... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
324c7fa... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
a0d9477... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
1cfdc20... [RISC-V] Infrastructure of synthesizing logical AND with co
f393f0f... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
2c0daa4... [PATCH v2 1/2] The following changes enable P8700 processor
eb95676... [RISC-V] Avoid multiple assignments to output object
001ff33... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
0468f67... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
f520787... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
a406f5d... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
f63c844... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
0c8455a... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
35eb922... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
3c80a35... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
6c6031d... [committed][RISC-V][PR target/120333] Remove bogus bext pat
db02e1f... [RISC-V] Fix false positive from Wuninitialized
0eff3cf... RISC-V: Fix the warning of temporary object dangling refere
e06e93d... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
9eead11... RISC-V: Support Zilsd code gen
30e7e3e... RISC-V: Add new operand constraint: cR
4c331a6... [RISC-V] Fix ICE due to bogus use of gen_rtvec
47c561c... [RISC-V] Avoid setting output object more than once in IOR/
f1c985c... RISC-V: Since the loop increment i++ is unreachable, the lo
ae1b1e6... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
8f135df... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
560c06a... Make end_sequence return the insn sequence
fa1c9fc... RISC-V: Reuse test name for vx combine test data [NFC]
965e1af... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
03cb5ca... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
0e65f50... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
b6d7b52... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
6784a16... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
fd9da05... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
e79595a... RISC-V: Adjust vx combine test case to avoid name conflict
2344488... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
1c7c6e2... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
0f1804c... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
65f1f1d... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
df337ed... RISC-V: Add augmented hypervisor series extensions.
dac3a0d... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
784cf1f... RISC-V: Regen riscv-ext.opt.urls
613572f... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
6a8edfa... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
2120b71... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
e06d638... RISC-V: Introduce riscv_ext_info_t to hold extension metada
6cf296c... RISC-V: Adjust riscv_can_inline_p
a430ef0... RISC-V: Generate extension table in documentation from risc
7abf721... RISC-V: Use riscv-ext.def to generate target options and va
7ac17ba... RISC-V: Introduce riscv-ext*.def to define extensions
e36df01... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
52e30b7... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
9c20668... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
98121fe... RISC-V: Support for zilsd and zclsd extensions.
198061e... testsuite: Fix RISC-V arch-52.c format issue.
3ae607e... RISC-V: Support RISC-V Profiles 23.
0e392bb... RISC-V: Support RISC-V Profiles 20/22.
24765f7... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
ad89ca4... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
f34c6e1... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
463920b... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
12f4e93... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
21b8a8d... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
6dc9157... RISC-V: Separate the test running of rvv vx_vf
c7a985b... [RISC-V][PR target/120137][PR target/120154] Don't create o
c1c086d... [PATCH] RISC-V: Minimal support for zama16b extension.
3c3f799... [RISC-V] Avoid unnecessary andi with -1 argument
7376527... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
759d682... [PATCH] RISC-V: Recognized svadu and svade extension
3049bc3... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
b486c90... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
e844422... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
329ce66... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
b427f1c... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
2a05aff... RISC-V: Add gr2vr cost helper function
8cc8438... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
a9338ad... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
29351e5... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
4888b2d... [V2][RISC-V] Trivial permutation constant derivation
339916f... [RISC-V] Adjust rvv tests after recent jump threading chang
1dcb387... [PATCH] RISC-V: Implment H modifier for printing the next r
b7a7d1f... [to-be-committed][RISC-V] Adjust testcases and finish regis
e879380... RISC-V: Remove unnecessary frm restore volatile define_insn
71d4df7... RISC-V: Allow different dynamic floating point mode to be m
73f1322... RISC-V: Fix missing implied Zicsr from Zve32x
97e8a2b... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
9d5aa2b... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
3c176c3... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
6021da7... RISC-V: Extract vector stepped for expand_const_vector [NFC
aadd08d... RISC-V: Extract vector duplicate for expand_const_vector [N
4508a2f... RISC-V: Extract vec_series for expand_const_vector [NFC]
5f8f9ad... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
2e07d3c... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
27346e9... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
70451a0... [riscv] vec_dup immediate constants in pred_broadcast expan
097eefd... [RISC-V][PR target/119865] Don't free ggc allocated memory
f9a84c7... [RISC-V][PR target/118410] Improve code generation for some
c4a9842... [RISC-V] Fix missed bext discovery
843877a... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
44f33e7... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
a0d2781... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
Summary of changes (added commits):
-----------------------------------
cd6efdb... RISC-V: Combine vec_duplicate + vwaddu.wv to vwaddu.wx on G
0201049... ISC-V: Add test for vec_duplicate + vwaddu.wv signed combin
6b3e1ae... Fixup merge conflict
3bf5567... [PATCH v2] RISC-V: Fix type of CFA during stack probe [PR12
036f356... [RISC-V][PR target/122147] Avoid creating (subreg (mem)) in
080fb4d... [PR target/118945][PATCH v3] RISC-V: Add 'prefer_agnostic'
b3a9023... [RISC-V][PR rtl-optimization/121937] Don't call neg_poly_in
7a1b48f... [RISC-V][PR target/122051] Fix pmode_reg_or_uimm5_operand f
15ea306... [RISC-V][PR target/122106] Add missing predicate on crc exp
1c0e36b... [PATCH][PR target/121778] RISC-V: Improve rotation detectio
ff5fe6a... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
2136b5d... RISC-V: Add missing define_insn_reservation to tt-ascalon-d
12ef1c3... [RISC-V][PR target/121983] Fix unprotected REGNO invocation
e2f1a28... RISC-V: Improve slide patterns recognition
c04f130... RISC-V: Only Save/Restore required registers for ILP32E/LP6
a339781... [RISC-V] Optimize clear-lowest-set-bit sequence when ctz is
3ff97d3... RISC-V: Correct lmul estimation
6dfaa88... RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for
ccaaf71... [PR tree-optimization/58727] Don't over-simplify constants`
3306783... RISC-V: Add test for vec_duplicate + vwmulu.vv signed combi
5f82563... RISC-V: Add test for vec_duplicate + vwsubu.vv signed combi
f50e6a9... RISC-V: Add test for vec_duplicate + vwaddu.vv signed combi
6038958... RISC-V: Combine vec_duplicate + vwaddu.vv to vwaddu.vx on G
1155cb2... RISC-V: Allow profiles input in '--with-arch' option.
fd28c51... RISC-V: Configure Profiles definitions in the definition fi
f4bc298... RISC-V: Imply zicsr for sdtrig and ssstrict extensions.
41f72dd... Widening-Mul: Refine build_and_insert_cast when rhs is cast
1efc182... RISC-V: Fix vendor intrinsic tests for disabled multilib co
68d01ef... RISC-V: Support vnclip idiom testcase [PR120378]
ca10dea... Match: Support SAT_TRUNC variant NARROW_CLIP
b65c2f9... [RISC-V] Adjust ABI specification in recently added Andes t
6c92582... RISC-V: Suppress cross CC sibcall optimization from vector
250a183... RISC-V: Add min/max patterns for ifcvt.
5b68975... ifcvt: Clarify if_info.original_cost.
9a467a7... RISC-V: Fix can_find_related_mode_p for VLS types
3ec5483... RISC-V: Fix typo in tt-ascalon-d8's pipeline description [P
86cc6a8... RISC-V: Add pattern for vector-scalar single widening float
7cb1fbc... RISC-V: Add pattern for vector-scalar dual widening floatin
292404d... RISC-V: Add pattern for vector-scalar single widening float
f85fe1f... RISC-V: Add pattern for vector-scalar widening floating-poi
91d9bd0... RISC-V: Adjust tt-ascalon-d8 branch cost
1ac4f1a... RISC-V: Add pattern for vector-scalar single-width floating
02e2f57... RISC-V: Add pattern for vector-scalar single-width floating
7e7b99a... RISC-V: Add pattern for vector-scalar single-width floating
cc55806... RISC-V: Add pattern for vector-scalar widening floating-poi
161dd9b... RISC-V: Add patterns for vector-scalar IEEE floating-point
e920c4c... gcc: introduce the dep_fusion pass
3da43d9... RISC-V: Add support for the XAndesvdot ISA extension.
5c723df... [RISC-V] Fix ordering of pipeline models
2479462... RISC-V: Add support for the XAndesvpackfph ISA extension.
a0ac3ac... RISC-V: Add test for vec_duplicate + vnmsub.vv unsigned com
ac28efe... RISC-V: Add test for vec_duplicate + vnmsub.vv signed combi
0b10063... RISC-V: Combine vec_duplicate + vnmsub.vv to vnmsub.vx on G
70d5fe8... dep_fusion: Fix if target does not have macro fusion [PR121
99827c2... gcc: introduce the dep_fusion pass
17ea4ff... RISC-V: Add support for the XAndesvsintload ISA extension.
14bf41e... RISC-V: Add support for the XAndesvbfhcvt ISA extension.
e1bd1ba... RISC-V: Add tt-ascalon-d8 pipeline description
0964598... [RISC-V] Adjust recently added test
d3e072d... RISC-V: Combine vec_duplicate + vmadd.vv to vmadd.vx on GR2
e78ed90... RISC-V: Allow errors to be suppressed when parsing architec
0acd8e5... RISC-V: Adjust the vmacc.vx combine test cases
9994c71... RISC-V: Add test for vec_duplicate + vmadd.vv unsigned comb
3509c9a... RISC-V: Add test for vec_duplicate + vmadd.vv signed combin
87199b0... RISC-V: Fix extension subset check in riscv_can_inline_p
15fe0d9... RISC-V: Add support for the XAndesbfhcvt ISA extension.
9ce705d... RISC-V: Add support for the XAndesperf ISA extension.
5def5b4... RISC-V: Add basic XAndes vendor extension support.
822db7e... RISC-V: Add pattern for vector-scalar floating-point max
91f730b... [RISC-V][PR target/121213] Avoid unnecessary sign extension
9116962... RISC-V: Fix is_vlmax_len_p and use for strided ops.
cea2296... RISC-V: Add Zbb extension sext testcase.
55e2baa... RISC-V: Update Zba 'shNadd.uw' testcase.`
30f79cd... RISC-V: Remove unused print_ext_doc_entry function [NFC]
b4a4a4c... [RISC-V] Improve initial RTL generation for SImode adds on
8d40f65... RISC-V: Add test case for unsigned scalar SAT_MUL form 4
8ac90c7... RISC-V: Add patterns for vector-scalar IEEE floating-point
2758230... RISC-V: Add test for vec_duplicate + vnmsac.vv unsigned com
96b4878... RISC-V: Add test for vec_duplicate + vnmsac.vv signed combi
f32be7a... RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on G
3c7d91d... RISC-V: Add pattern for vector-scalar floating-point min
2945f75... Remove xfail marker on RISC-V test
41d5505... RISC-V: testsuite: Fix vf_vfmul and vf_vfrdiv
31dd9b9... More RISC-V testsuite hygiene
55c0639... [committed] RISC-V Testsuite hygiene
4bcec61... [PATCH] RISC-V: Add pattern for reverse floating-point divi
b35987c... [PATCH] RISC-V: Add pattern for vector-scalar single-width
44627d0... Fix RISC-V bootstrap
3f12525... RISC-V: Add test for vec_duplicate + vmacc.vv unsigned comb
0a60a40... RISC-V: Add test for vec_duplicate + vmacc.vv signed combin
70dd601... RISC-V: Combine vec_duplicate + vmacc.vv to vmacc.vx on GR2
87ce970... RISC-V: Replace deprecated FUNCTION_VALUE/LIBCALL_VALUE mac
d8368df... Fix invalid right shift count with recent ifcvt changes
dd14b91... [PR rtl-optimization/120553] Improve selecting between cons
9cf545f... RISC-V: Add testcase for scalar unsigned SAT_MUL form 3
1ebaea7... RISC-V: testsuite: Fix DejaGnu support for riscv_zvfh
72750aa... [PR target/121213] Avoid unnecessary constant load in amosw
fd391fa... regrename: treat writes as reads for fused instruction pair
7c4a8c7... ira: tie output allocnos for fused instruction pairs
e48735b... [PATCH] RISC-V: Fix block matching in arch-canonicalize [PR
734eca2... RISC-V: Update the comments of vx combine [NFC]
8e38b8d... RISC-V: Add missed DONE for vx combine pattern [NFC]
8f57a53... RISC-V: MIPS prefetch extensions for MIPS RV64 P8700 and ca
4cb6706... [PR target/119275][RISC-V] Avoid calling gen_lowpart in cas
f6809e0... [RISC-V][PR target/121531] Cover missing insn types in p400
cef6d72... [RISC-V][PR target/121160] Avoid bogus force_reg call
20918a8... [RISC-V][PR target/121113] Handle HFmode in various insn re
00ef6ba... RISC-V: RISC-V: Add test for vec_duplicate + vmerge.vvm com
6872856... RISC-V: Combine vec_duplicate + vmerge.vv to vmerge.vx on G
53ee95f... RISC-V: Expand const_vector with 2 elts per pattern.
db28ef6... Improve initial code generation for addsi/adddi
d0230a0... Don't run tests requiring "B" on designs without "B"
8257271... RISC-V: Add testcase for scalar unsigned SAT_MUL form 2
f3e904c... RISC-V: Refactor the vec_duplicate cost on gpr/fpr2vr-cost
c8a70b2... RISC-V: Read extension data from riscv-ext*.def for arch-ca
07b8e32... RISC-V: Support -march=unset
e8f3ac0... RISC-V: Fix scalar code-gen of unsigned SAT_MUL
f546227... RISC-V: Add testcases for signed avg ceil vx combine
8ef5e8a... RISC-V: Adding H to the canonical order [PR121312]
164a85d... RISC-V: Add testcases for unsigned avg ceil vx combine.
fdc566a... RISC-V: Generate -mcpu and -mtune options from riscv-cores.
1a1a765... RISC-V: Remove use of structured binding to fix compiler wa
7d0c658... RISC-V: Add test cases for mul based unsigned scalar SAT_MU
9f52e74... RISC-V: Add test case for vaadd.vx combine polluting VXRM
7671400... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
9575fc1... RISC-V: Add test for vec_duplicate + vaadd.vv combine case
5c4ef2d... RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2
7636483... RISC-V: Fix another vf FP16 combine run test failures
9e24c11... RISC-V: riscv-ext.def: Add allocated group IDs and group bi
963a83d... RISC-V: Prepare dynamic LMUL heuristic for SLP.
bd4cd86... RISC-V: Remove user-level interrupts
2d24fbe... RISC-V: Add support for resumable non-maskable interrupt (R
5b1be4b... riscv: testsuite: Fix misalignment check.
077b218... RISC-V: Add test case for vx combine polluting VXRM
cf194bc... RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr
6c0993c... RISC-V: Rework broadcast handling [PR121073].
cb813e3... RISC-V: testsuite: Fix vx_vf_*run-1-f16.c run tests.
3da86ad... Change bellow in comments to below
0758b4e... [RISC-V] Restrict generic-vector-ooo DFA
9fbe96e... [RISC-V] Add missing insn types to xiangshan.md and mips-p8
d2ee98c... RISC-V: Add test for vec_duplicate + vaaddu.vv combine for
4263f17... RISC-V: Allow VLS DImode for sat_op vx DImode pattern
9474861... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
f3b6b6f... RISC-V: Add test for vec_duplicate + vaaddu.vv combine case
c798ab3... RISC-V: Combine vec_duplicate + vaaddu.vv to vaaddu.vx on G
bb91212... RISC-V: Add testcase for unsigned scalar SAT_ADD form 8 and
d48bd8f... RISC-V: Refine the test case for vector avg_floor and avg_c
a8f81e8... RISC-V: Add ashiftrt operand 2 for vector avg_floor and avg
9c85a3c... [PATCH] RISC-V: Vector-scalar widening negate-multiply-(sub
9dfc310... [PATCH] RISC-V: prevent NULL_RTX dereference in riscv_macro
a3c1aea... RISC-V: Support RVVDImode for avg3_ceil auto vect
d703817... RISC-V: Fix vsetvl merge rule.
c27d0b1... RISC-V: Refine the scalar SAT_* test cases
223b5e2... RISC-V: Support RVVDImode for avg3_floor auto vect
4661020... [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.
13c65e0... RISC-V: Add testcase for rv32 SAT_MUL from uint64
a750800... [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtrac
f4fdee4... RISC-V: Add testcases for unsigned vector SAT_SUB form 11 a
51a049f... RISC-V: Make zero-stride load broadcast a tunable.
8655a4b... [RISC-V] Detect new fusions for RISC-V
9823a6a... RISCV: Remove the v extension requirement for sat scalar ru
ba456f4... RISC-V: Add test for vec_duplicate + vssub.vv combine case
13bfa93... RISC-V: Add test for vec_duplicate + vssub.vv combine case
50e3ef0... RISC-V: Combine vec_duplicate + vssub.vv to vssub.vx on GR2
4959c80... [PATCH] RISC-V: Enable zvfh for vector-scalar half-float ru
0692fe7... [PATCH] RISC-V: Adjust testdata for unsigned vector SAT_SUB
1d2c4b9... [RISC-V][PR target/120642] Avoid propagating constant AVL f
eaa4d0b... RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
603c77e... RISC-V: Do not use vsetivli for THeadVector.
5e6275f... RISC-V: Ignore non-types in builtin function hash.
5e99664... [committed][RISC-V] Fix testsuite fallout from check-functi
4faca02... RISC-V: Add test cases for unsigned scalar SAT_MUL from uin
71852aa... RISC-V: Implement unsigned scalar SAT_MUL from uint128_t
512dada... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
784e08c... RISC-V: Add test for vec_duplicate + vsadd.vv combine case
f85bccd... RISC-V: Combine vec_duplicate + vsadd.vv to vsadd.vx on GR2
34d0d36... [RISC-V] Add basic instrumentation to fusion detection
4af7efa... RISC-V: Add testcases for signed scalar SAT_ADD IMM form 2
aaba6bd... Refactor record_function_versions.
3a8762c... [RISC-V][PR target/118886] Refine when two insns are signal
29e0bf3... RISC-V: testsuite: Skip tests providing -march/-mcpu for IL
1eb6c4f... [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped
d3bb888... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
892fcd2... RISC-V: Add test for vec_duplicate + vssubu.vv combine case
ef6dbb3... RISC-V: Reconcile the existing test due to cost model chang
7c6e572... RISC-V: Combine vec_duplicate + vssubu.vv to vssubu.vx on G
5b557e4... RISC-V: Ignore -Oz for most rvv testcase [NFC]
35c93d8... RISC-V: Primary vector pipeline model for sifive 7 series
953e550... RISC-V: Adding B ext, fp16 and missing scalar instruction t
2c52c26... RISC-V: Vector-scalar negate-multiply-(subtract-)accumulate
d3fc411... RISC-V: Refactor the function bitmap_union_of_preds_with_en
556e7e2... RISC-V: Add pipeline-checker script
2d9da64... [RISC-V][PR target/119971] Avoid losing shift count masking
04cb23c... RISC-V: update prepare_ternary_operands to handle vector-sc
113fda1... RISC-V: Fix build issue
d485714... RISC-V: Add comment and reorder the the include files in ri
13796fc... RISC-V: Add Profiles RVA/B23S64 support.
0aece63... RISC-V: Add patterns for vector-scalar multiply-(subtract-)
ab2166d... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
8c2c52d... RISC-V: Add test for vec_duplicate + vsaddu.vv combine case
1fe100e... RISC-V: Combine vec_duplicate + vsaddu.vv to vsaddu.vx on G
d9f945f... [RISC-V][PR target/118241] Fix data prefetch predicate/cons
2aacb8f... RISC-V: Fix ICE for expand_select_vldi [PR120652]
d6bc248... [RISC-V] Force several tests to use rocket tuning
254a6cd... [PATCH] RISC-V: Use builtin clz/ctz when count_leading_zero
b49ba3c... RISC-V: Add test for vec_duplicate + vminu.vv combine case
faa5a0d... RISC-V: Add test for vec_duplicate + vminu.vv combine case
c8087fe... RISC-V: Combine vec_duplicate + vminu.vv to vminu.vx on GR2
41343fa... RISC-V: Add generic tune as default.
db00246... RISC-V: Use riscv_2x_xlen_mode_p [NFC]
34fc216... RISC-V: Adding cost model for zilsd
78ae220... RISC-V: Add test for vec_duplicate + vmin.vv combine case 1
2026be0... RISC-V: Add test for vec_duplicate + vmin.vv combine case 0
78c02e3... RISC-V: Combine vec_duplicate + vmin.vv to vmin.vx on GR2VR
75e30c9... [PATCH v1] RISC-V: Use scratch reg for loop control
b2c5e5d... RISC-V: Add -fno-pie flags to testcases
ee71dcf... RISC-V: Refine VX combine test case 0 to avoid code duplica
d72c0f9... RISC-V: Update Profiles string in RV23.
1702d4b... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
88dc996... RISC-V: Add test for vec_duplicate + vmaxu.vv combine case
eb245c6... RISC-V: Combine vec_duplicate + vmaxu.vv to vmaxu.vx on GR2
42dd07d... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
1112f23... RISC-V: Add test for vec_dup + vmax.vv combine case 1 with
7725094... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
2807d58... RISC-V: Add test for vec_dup + vmax.vv combine case 0 with
7ded99c... RISC-V: Combine vec_duplicate + vmax.vv to vmax.vx on GR2VR
55d6bf2... RISC-V: Prevent speculative vsetvl insn scheduling
87a91f7... RISC-V: Add patterns for vector-scalar negate-(multiply-add
b257752... RISC-V: testsuite: fix an obvious build error
d7c0cae... RISC-V: Regen riscv-ext.texi [NFC]
a6fa625... RISC-V: Add test for vec_duplicate + vremu.vv combine case
0f36ec2... RISC-V: Add test for vec_duplicate + vremu.vv combine case
dd66b8e... RISC-V: Reconcile the existing test for vremu.vx combine
68892a7... RISC-V: Combine vec_duplicate + vremu.vv to vremu.vx on GR2
106a5b6... [RISC-V] Enable more if-conversion on RISC-V
dfdba84... RISC-V: Add test for vec_duplicate + vrem.vv combine case 1
119fcab... RISC-V: Add test for vec_duplicate + vrem.vv combine case 0
a863116... RISC-V: Reconcile the existing test for vrem.vx combine
91d7d08... RISC-V: Combine vec_duplicate + vrem.vv to vrem.vx on GR2VR
b7c0370... RISC-V: frm/mode-switch: robustify call_insn backtracking [
eaad234... RISC-V: frm/mode-switch: Reduce FRM restores on DYN transit
e792a4d... RISC-V: frm/mode-switch: remove dubious frm edge insertion
a412b30... RISC-V: frm/mode-switch: remove TARGET_MODE_CONFLUENCE
81d6dfe... [RISC-V] Handle 32bit operands in condition for conditional
f33f7c5... [to-be-committed][RISC-V] Handle 32bit operands in conditio
d96055f... RISC-V: Reconcile the existing test for vdivu.vx combine
327bbd4... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
5aeb35f... RISC-V: Add test for vec_duplicate + vdivu.vv combine case
f650868... RISC-V: Combine vec_duplicate + vidvu.vv to vdivu.vx on GR2
170b05d... RISC-V: Support -mcpu for XiangShan Kunminghu cpu.
3b4faa2... [RISC-V] Improve signed division by 2^n
d8b5824... RISC-V: Don't use structured binding in riscv-common.cc
4d08c11... RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
35b6592... [RISC-V] Improve sequences to generate -1, 1 in some cases.
00797b0... RISC-V: Support Ssu64xl extension.
8b3aef1... RISC-V: Support Sstvecd extension.
6f82f85... RISC-V: Support Sstvala extension.
ba09a6b... RISC-V: Support Sscounterenw extension.
7fbd8c3... RISC-V: Support Ssccptr extension.
c4bfa6c... RISC-V: Support Smrnmi extension.
3ba2215... RISC-V: Support Sm/scsrind extensions.
85353d4... RISC-V: Update extension defination.
210d65a... [PATCH] RISC-V: Imply zicsr for svade and svadu extensions.
e7fd3f3... [PATCH v2] RISC-V: Add svbare extension.
d004182... RISC-V: Leverage get_vector_binary_rtx_cost to avoid code d
df3172f... RISC-V: Add Shlcofideleg extension.
7c4f86d... RISC-V: Reconcile the existing test for vdiv.vx combine
6cc972e... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 1
c38c393... RISC-V: Add test for vec_duplicate + vdiv.vv combine case 0
14700cc... RISC-V: Combine vec_duplicate + vidv.vv to vdiv.vx on GR2VR
cb84104... RISC-V: Use helper function to get FPR to VR move cost
c9ae6a2... RISC-V: Add pattern for vector-scalar multiply-add/sub [PR1
1eca67a... [PATCH] RISC-V: Add smcntrpmf extension.
31d47cf... RISC-V: Adjust build rule for gen-riscv-ext-opt and gen-ris
66851c7... RISC-V: Implement full-featured iterator for riscv_subset_l
b9e9f98... [PATCH] testsuite: RISC-V: Fix the typo in param-autovec-mo
617b47a... RISC-V: Fix line too long format issue for autovect.md [NFC
ed59a0b... RISC-V: Add test cases for avg_ceil vaadd implementation
f9199f3... RISC-V: Reconcile the existing test for avg_ceil
b45f075... RISC-V: Leverage vaadd.vv for signed standard name avg_ceil
c9851de... RISC-V: Add minimal support of double trap extension 1.0
8910052... RISC-V: Add test for vec_duplicate + vmul.vv combine case 1
d351ef7... RISC-V: Add test for vec_duplicate + vmul.vv combine case 0
8385aa3... RISC-V: Combine vec_duplicate + vmul.vv to vmul.vx on GR2VR
154bd42... RISC-V: Avoid division by zero in check_builtin_call [PR120
dcfd64a... RISC-V: Add test cases for avg_floor vaadd implementation
7395d85... RISC-V: Reconcile the existing test for avg_floor
fd558b7... RISC-V: Leverage vaadd.vv for signed standard name avg_floo
c8369a9... [RISC-V] Add andi+bclr synthesis
74d782a... RISC-V: Add test for vec_duplicate + vxor.vv combine case 1
4f8f22a... RISC-V: Add test for vec_duplicate + vxor.vv combine case 0
7899526... RISC-V: Combine vec_duplicate + vxor.vv to vxor.vx on GR2VR
9b11324... RISC-V: Add testcases for signed vector SAT_ADD IMM form 1
5a79df6... RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IM
de9c3a5... [RISC-V] shift+and+shift for logical and synthesis
3c66d5d... RISC-V: Add test for vec_duplicate + vor.vv combine case 1
d37d366... RISC-V: Add test for vec_duplicate + vor.vv combine case 0
798b899... RISC-V: Combine vec_duplicate + vor.vv to vor.vx on GR2VR c
77192f9... RISC-V: Support CPUs in -march.
df37c18... RISC-V: Add autovec mode param.
539ffb6... RISC-V: Default-initialize variable.
2311953... RISC-V: Fix some dynamic LMUL costing.
7532fea... [RISC-V] Clear both upper and lower bits using 3 shifts
1609201... [PATCH][RISC-V][PR target/70557] Improve storing 0 to memor
9c26815... [PATCH] testsuite: RISC-V: Update the cset-sext-sfb/zba-sll
7f71ec3... [RISC-V] Clear high or low bits using shift pairs
14032ff... [RISC-V] Improve (x << C1) + C2 split code
c0e3e4d... [RISC-V][PR target/120368] Fix 32bit shift on rv64
4bbd7d4... RISC-V: Add test for vec_duplicate + vand.vv combine case 1
f5f7e0f... RISC-V: Add test for vec_duplicate + vand.vv combine case 0
d581894... RISC-V: RISC-V: Combine vec_duplicate + vand.vv to vand.vx
2d65845... [RISC-V] Infrastructure of synthesizing logical AND with co
7337427... [PATCH v2 2/2] MIPS p8700 doesn't have vector extension and
9f41454... [PATCH v2 1/2] The following changes enable P8700 processor
b71e434... [RISC-V] Avoid multiple assignments to output object
4aea2cc... RISC-V: Tweak the asm check test of vx combine on GR2VR cos
4d7e1e8... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
db456ad... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
ce93cab... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
03e5e07... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
c5e4877... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
970f8be... RISC-V: Add test for vec_duplicate + vrsub.vv combine case
bc2358c... RISC-V: Combine vec_duplicate + vrsub.vv to vrsub.vx on GR2
059a65a... [committed][RISC-V][PR target/120333] Remove bogus bext pat
621e567... [RISC-V] Fix false positive from Wuninitialized
4934434... RISC-V: Fix the warning of temporary object dangling refere
595a41d... RISC-V: Rename conflicting variables in gen-riscv-ext-texi.
1d61114... RISC-V: Support Zilsd code gen
d098416... RISC-V: Add new operand constraint: cR
a8aec95... [RISC-V] Fix ICE due to bogus use of gen_rtvec
47d786d... [RISC-V] Avoid setting output object more than once in IOR/
625c64e... RISC-V: Since the loop increment i++ is unreachable, the lo
f8d49ba... RISC-V: Avoid scalar unsigned SAT_ADD test data duplication
59353f7... Partial cherry-pick of 4dd13988c93c24ba3605f4b9cafc97515c34
c8f3582... Make end_sequence return the insn sequence
2ee0372... RISC-V: Reuse test name for vx combine test data [NFC]
9f7bbb6... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
f06c232... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
6aab85f... RISC-V: Add test for vec_duplicate + vsub.vv combine case 1
cf19efc... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
08d0138... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
777f3f5... RISC-V: Add test for vec_duplicate + vsub.vv combine case 0
ca9a2cc... RISC-V: Adjust vx combine test case to avoid name conflict
788b0b3... RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combin
959ef69... RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR
c9ec3ca... [RISC-V][PR target/120223] Don't use bset/binv for XTHEADBS
58832b4... RISC-V: Fix uninit riscv_subset_list::m_allow_adding_dup is
98c76d6... RISC-V: Add augmented hypervisor series extensions.
96f8d08... RISC-V: Drop duplicate build rule for riscv-ext.opt [NFC]
02feb0a... RISC-V: Regen riscv-ext.opt.urls
cbca3d6... RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_inf
b5e5673... RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_
f520e1a... RISC-V: Drop riscv_implied_info and riscv_combine_info in f
03a0b46... RISC-V: Introduce riscv_ext_info_t to hold extension metada
80abf2b... RISC-V: Adjust riscv_can_inline_p
7b8c03d... RISC-V: Generate extension table in documentation from risc
c80f7cc... RISC-V: Use riscv-ext.def to generate target options and va
67fe251... RISC-V: Introduce riscv-ext*.def to define extensions
1c82aad... RISC-V: Add testcases for vector unsigned integer SAT_ADD f
5f6f46d... RISC-V: Add testcases for scalar unsigned integer SAT_ADD f
5698c69... RISC-V: Minimal support for ssnpm, smnpm and smmpm extensio
dc21dae... RISC-V: Support for zilsd and zclsd extensions.
b6f9046... testsuite: Fix RISC-V arch-52.c format issue.
0199242... RISC-V: Support RISC-V Profiles 23.
512416e... RISC-V: Support RISC-V Profiles 20/22.
1b49bf1... [V2][RISC-V] Synthesize more efficient IOR/XOR sequences
d72a139... [PATCH v2] RISC-V: Use vclmul for CRC expansion if availabl
7969760... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
e56b0cc... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
e1ad6ec... RISC-V: Add testcases for vec_duplicate + vadd.vv combine c
fa7c218... RISC-V: Rename VX_BINARY test helper to VX_BINARY_CASE_0
57ffa78... RISC-V: Separate the test running of rvv vx_vf
42b244d... [RISC-V][PR target/120137][PR target/120154] Don't create o
f341dc9... [PATCH] RISC-V: Minimal support for zama16b extension.
ac8523d... [RISC-V] Avoid unnecessary andi with -1 argument
40b0f99... [PATCH] RISC-V: Minimal support for sdtrig and ssstrict ext
f7ff1dd... [PATCH] RISC-V: Recognized svadu and svade extension
50daa71... [RISC-V][PR middle-end/114512] Recognize more bext idioms f
b124e93... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
9187016... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
de6572d... RISC-V: Add testcases for vec_duplicate + vadd.vv combine w
fe9f4cf... RISC-V: Combine vec_duplicate + vadd.vv to vadd.vx on GR2VR
3d5f2b4... RISC-V: Add gr2vr cost helper function
7b5b49f... RISC-V: Add new option --param=gpr2vr-cost= for rvv insn
1a45d5c... RISC-V: Fix gcc.target/riscv/predef-19.c [PR120054]
ee192c1... RISC-V: Apply clang-format to genrvv-type-indexer.cc [NFC]
f08eafd... [V2][RISC-V] Trivial permutation constant derivation
c9c5f13... [RISC-V] Adjust rvv tests after recent jump threading chang
9e77f9c... [PATCH] RISC-V: Implment H modifier for printing the next r
578cf93... [to-be-committed][RISC-V] Adjust testcases and finish regis
18c5238... RISC-V: Remove unnecessary frm restore volatile define_insn
e229173... RISC-V: Allow different dynamic floating point mode to be m
9fcbe24... RISC-V: Fix missing implied Zicsr from Zve32x
3e08742... RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensio
889bd8c... RISC-V: Add intrinsics support for SiFive Xsfvcp extensions
8c4be6a... RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS
16d46b7... RISC-V: Extract vector stepped for expand_const_vector [NFC
e066eff... RISC-V: Extract vector duplicate for expand_const_vector [N
ccdcf87... RISC-V: Extract vec_series for expand_const_vector [NFC]
3b73e0c... RISC-V: Extract vec_duplicate for expand_const_vector [NFC]
d772530... [PATCH] RISC-V: Imply C from Zca whenever possible [PR11912
7f8f524... [PATCH] [RISC-V]Support -mcpu for Xuantie cpu
d8e409a... [riscv] vec_dup immediate constants in pred_broadcast expan
47518d2... [RISC-V][PR target/119865] Don't free ggc allocated memory
7022dee... [RISC-V][PR target/118410] Improve code generation for some
559c051... [RISC-V] Fix missed bext discovery
933bc9d... [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC
4b1d120... [PATCH] [RISC-V] Tune for removal unnecessary sext in built
a759907... [PATCH] RISC-V: Do not free a riscv_arch_string when handli
fad7547... c++/modules: Stream BASELINK_OPTYPE [PR122381] (*)
0186567... Daily bump. (*)
5b7639b... vect: Fix operand swapping on complex multiplication detect (*)
c250cb5... LoongArch: Only allow valid binary op when optimize conditi (*)
b54cc5a... Daily bump. (*)
f558f45... LoongArch: Standard instruction template fnmam4 correction (*)
f092f60... Daily bump. (*)
aad8389... Daily bump. (*)
402d578... c++: mem-initializer-id qualified name lookup is type-only (*)
df569c0... c++: base-specifier name lookup is type-only [PR122192] (*)
fc900b2... c++/modules: Use containing type as key for all member lamb (*)
18540d2... Daily bump. (*)
e55dcff... phiopt: Fix up DEBUG_EXPR_DECL creation in spaceship_replac (*)
9b1141f... [RISC-V][PR target/120674] Avoid division by zero in dwarf (*)
f3d0c95... AArch64: Extend intrinsics framework to account for merging (*)
f737b65... x86: Compile builtin-copysign-8b.c with -mtune=generic (*)
8980668... Daily bump. (*)
1be9c04... x86-64: Use `movsxd` to perform SI-to-DI extension in Intel (*)
1e4a2d0... [aarch64] [testsuite] tolerate alternate insn selection [PR (*)
043b852... Daily bump. (*)
2f881d8... Fortran: fix "unstable" interfaces of external procedures [ (*)
857ab30... Fortran: fix issue with I/O of array pointer [PR107968] (*)
22a1897... Daily bump. (*)
e4ee38a... Ada: Fix segfault on file without final EOL with -gnatyc (*)
e501f31... Ada: Fix other instances of incorrect String lower bound in (*)
ceb6f79... x86: builtin-fabs-2.c: Also scan (%edi) for x32 (*)
ff3e6f4... tree-object-size.cc: Fix assert constant offset in check_fo (*)
653977c... x86: Optimize copysign (x, const_double) (*)
0ec0def... Daily bump. (*)
96c8dc3... testsuite: arm: [MVE] Relax expected code for vbicq_f [PR12 (*)
b0bb656... Daily bump. (*)
f8f8e79... c++: Fix up RAW_DATA_CST handling in braced_list_to_string (*)
9a9470a... i386: Correct cpu codename value for unknown model number (*)
ef9de83... Daily bump. (*)
eccd6fb... arm: [MVE] Fix operands order in vbicq_f [PR122223] (*)
7bfcc84... aarch64: Fix ICE when op2 is zero for SVE2 saturating add i (*)
ab801b6... Daily bump. (*)
be2f50c... hurd: Add OPTION_GLIBC_P and OPTION_GLIBC (*)
e41abec... libstdc++: Remove undeclared macros from configure.ac [PR12 (*)
9aafd06... libstdc++: Fix unsafe comma operators in <random> [PR122062 (*)
2eec075... Ada: Fix spurious warning for renaming of component of VFA (*)
ffb5591... Daily bump. (*)
6caf0a5... Daily bump. (*)
811d543... Daily bump. (*)
9f6cae5... x86: Cast stride to __PTRDIFF_TYPE__ for AMX-MOVRS intrinsi (*)
6af0281... Daily bump. (*)
fc76690... Error out stack-protector unavailability on AIX (*)
e203de0... Daily bump. (*)
052094e... libstdc++-v3: Enable features for RTEMS (based on GCC 15) (*)
5b999c3... aarch64: Fix pmsdsfr_el1 encoding (*)
839618f... aarch64, testsuite: Add -fchecking to test options [PR12177 (*)
b8f35ed... i386: Correct ISA set for Panther Lake and Diamond Rapids (*)
fbc57d4... Daily bump. (*)
fb9d8d1... c++: pointer to auto member function [PR120757] (*)
363edb3... gimplify: Fix up side-effect handling in 2nd __builtin_c[lt (*)
a65420e... gimplify: Fix up __builtin_c[lt]zg gimplification [PR122188 (*)
e088f42... stmt: Handle %cc[name] in resolve_asm_operand_names [PR1221 (*)
5d74b47... widening_mul: Reset flow sensitive info in maybe_optimize_g (*)
2806148... i386: Remove AMX-TRANSPOSE from Diamond Rapids (*)
4be35c4... Daily bump. (*)
20853b8... match.pd: Do not canonicalize division by power 2 for {ROUN (*)
afb2858... Daily bump. (*)
13ac53b... Daily bump. (*)
c8acafb... [PATCH] RISC-V: Detect wrap in shuffle_series_pattern [PR12 (*)
05f6770... Daily bump. (*)
7b462d3... Daily bump. (*)
296904b... AVR: target/122222 - Add modules for __floatsidf, __floatun (*)
9120226... AVR: target/122220 - Let (int32_t) -0x1p31L return INT32_MI (*)
9163238... AVR: target/122210 - Add double -> fixed-point conversions. (*)
5ce2681... AVR: target/122210 - Add fixed-point -> double conversions. (*)
3b70c3d... Daily bump. (*)
ddf3423... [PATCH v2] RISC-V: fix __builtin_round NaN handling [PR tar (*)
092eac0... Daily bump. (*)
e4f5a5b... AVR: target/122187 - Don't clobber recog_data.operand[] in (*)
774ee96... Daily bump. (*)
0d83aa6... AVR/LibF7: Implement sincos. (*)
038bb0f... AVR/LibF7: target/122177 - fix fmin / fmax return value for (*)
f2eabd3... AVR: Speed up IEEE double comparisons. (*)
21e75aa... Daily bump. (*)
4cb36bc... Daily bump. (*)
90343ac... Add testcase for PR ada/113536 (*)
d731697... Ada: Remove useless Makefile variable (*)
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