[gcc(refs/vendors/riscv/heads/gcc-15-with-riscv-opts)] RISC-V: Combine vec_duplicate + vwaddu.wv to vwaddu.wx on GR2VR cost

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:cd6efdbdcbab5e06188775fcf179d20aed9c69bd

commit cd6efdbdcbab5e06188775fcf179d20aed9c69bd
Author: Pan Li <pan2...@intel.com>
Date:   Fri Sep 26 23:08:20 2025 +0800

    RISC-V: Combine vec_duplicate + vwaddu.wv to vwaddu.wx on GR2VR cost
    
    This patch would like to combine the vec_duplicate + vwaddu.wv to the
    vwaddu.wx.  From example as below code.  The related pattern will depend
    on the cost of vec_duplicate from GR2VR.  Then the late-combine will
    take action if the cost of GR2VR is zero, and reject the combination
    if the GR2VR cost is greater than zero.
    
    Assume we have asm code like below, GR2VR cost is 0.
    
    Before this patch:
      11       beq a3,zero,.L8
      12       vsetvli a5,zero,e32,m1,ta,ma
      13       vmv.v.x v2,a2
      ...
      16   .L3:
      17       vsetvli a5,a3,e32,m1,ta,ma
      ...
      22       vwaddu.wv v1,v2,v3
      ...
      25       bne a3,zero,.L3
    
    After this patch:
      11       beq a3,zero,.L8
      ...
      14    .L3:
      15       vsetvli a5,a3,e32,m1,ta,ma
      ...
      20       vwaddu.wx v1,a2,v3
      ...
      23       bne a3,zero,.L3
    
    Unfortunately, and similar as vwaddu.vv, only widening from uint32_t to
    uint64_t has the necessary zero-extend during combine, we loss the extend
    op after expand for any other types.
    
    gcc/ChangeLog:
    
            * config/riscv/autovec-opt.md (*widen_waddu_wx_<mode>): Add new
            pattern to match vwaddu.wx.
    
    Signed-off-by: Pan Li <pan2...@intel.com>
    (cherry picked from commit 4e2a2d6ad2d1bfe1269bc78da4251814505eb42e)

Diff:
---
 gcc/config/riscv/autovec-opt.md | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index a5eb49cc81ed..d5950ebe3b6b 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1911,6 +1911,26 @@
   }
   [(set_attr "type" "viwalu")])
 
+(define_insn_and_split "*widen_waddu_wx_<mode>"
+ [(set (match_operand:VWEXTI_D       0 "register_operand")
+       (any_widen_binop:VWEXTI_D
+        (vec_duplicate:VWEXTI_D
+          (any_extend:<VEL>
+            (match_operand:<VSUBEL> 2 "register_operand")))
+          (match_operand:VWEXTI_D   1 "register_operand")))]
+  "TARGET_VECTOR && TARGET_64BIT && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+  {
+    insn_code icode = code_for_pred_single_widen_scalar (PLUS, ZERO_EXTEND,
+                                                        <MODE>mode);
+    riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
+
+    DONE;
+  }
+  [(set_attr "type" "viwalu")])
+
 ;; 
=============================================================================
 ;; Combine vec_duplicate + op.vv to op.vf
 ;; Include