https://gcc.gnu.org/g:6fc2bb35f04c208ce8976e4d55aa17e40481568c
commit 6fc2bb35f04c208ce8976e4d55aa17e40481568c Author: Michael Meissner <[email protected]> Date: Tue Nov 4 19:45:29 2025 -0500 Revert changes Diff: --- gcc/config.gcc | 19 - gcc/config/rs6000/float16.cc | 335 ---------- gcc/config/rs6000/float16.md | 1263 ----------------------------------- gcc/config/rs6000/predicates.md | 102 --- gcc/config/rs6000/rs6000-builtin.cc | 20 - gcc/config/rs6000/rs6000-c.cc | 15 - gcc/config/rs6000/rs6000-call.cc | 40 -- gcc/config/rs6000/rs6000-cpus.def | 15 +- gcc/config/rs6000/rs6000-protos.h | 16 - gcc/config/rs6000/rs6000.cc | 182 +---- gcc/config/rs6000/rs6000.h | 20 - gcc/config/rs6000/rs6000.md | 3 - gcc/config/rs6000/rs6000.opt | 8 - gcc/config/rs6000/t-rs6000 | 4 - libgcc/config.host | 12 - libgcc/config/rs6000/sfp-machine.h | 50 -- libgcc/config/rs6000/t-bfloat16 | 30 - libgcc/config/rs6000/t-both-fp16 | 28 - libgcc/config/rs6000/t-float16 | 31 - libgcc/configure | 44 -- libgcc/configure.ac | 20 - libstdc++-v3/include/std/limits | 7 - 22 files changed, 24 insertions(+), 2240 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index ad8f0bd4e26c..a753c018ae1c 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -533,7 +533,6 @@ powerpc*-*-*) extra_objs="rs6000-string.o rs6000-p8swap.o rs6000-logue.o" extra_objs="${extra_objs} rs6000-call.o rs6000-pcrel-opt.o" extra_objs="${extra_objs} rs6000-builtins.o rs6000-builtin.o" - extra_objs="${extra_objs} float16.o" extra_headers="ppc-asm.h altivec.h htmintrin.h htmxlintrin.h" extra_headers="${extra_headers} bmi2intrin.h bmiintrin.h" extra_headers="${extra_headers} xmmintrin.h mm_malloc.h emmintrin.h" @@ -5799,24 +5798,6 @@ case "${target}" in elif test x$with_long_double_format = xibm; then tm_defines="${tm_defines} TARGET_IEEEQUAD_DEFAULT=0" fi - - # Test if we should enable 16-bit floating point on the platforms - # where we can support __bfloat16 and _Float16. - if test x$with_powerpc_float16 = xyes; then - tm_defines="${tm_defines} POWERPC_FLOAT16_DEFAULT=1" - - elif test x$with_powerpc_16bit_floating_point = xyes; then - tm_defines="${tm_defines} POWERPC_FLOAT16_DEFAULT=0" - fi - - # Test if we should disable the warning about passing - # and returning 16-bit floating point values. - if test x$with_powerpc_float16_disable_warning = xyes; then - tm_defines="${tm_defines} POWERPC_FLOAT16_DISABLE_WARNING=1" - - elif test x$with_powerpc_float16_disable_warning = xno; then - tm_defines="${tm_defines} POWERPC_FLOAT16_DISABLE_WARNING=0" - fi ;; s390*-*-*) diff --git a/gcc/config/rs6000/float16.cc b/gcc/config/rs6000/float16.cc deleted file mode 100644 index 2c7b6278a16a..000000000000 --- a/gcc/config/rs6000/float16.cc +++ /dev/null @@ -1,335 +0,0 @@ -/* Subroutines for the C front end on the PowerPC architecture. - Copyright (C) 2002-2025 Free Software Foundation, Inc. - - Contributed by Zack Weinberg <[email protected]> - and Paolo Bonzini <[email protected]> - - This file is part of GCC. - - GCC is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published - by the Free Software Foundation; either version 3, or (at your - option) any later version. - - GCC is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with GCC; see the file COPYING3. If not see - <http://www.gnu.org/licenses/>. */ - -/* 16-bit floating point support. */ - -#include "config.h" -#include "system.h" -#include "coretypes.h" -#include "backend.h" -#include "rtl.h" -#include "tree.h" -#include "memmodel.h" -#include "tm_p.h" -#include "stringpool.h" -#include "expmed.h" -#include "optabs.h" -#include "regs.h" -#include "insn-attr.h" -#include "flags.h" -#include "attribs.h" -#include "explow.h" -#include "expr.h" -#include "common/common-target.h" -#include "rs6000-internal.h" - -/* Expand a 16-bit vector operation: - - ICODE: Operation to perform. - RESULT: Result of the operation. - OP1: Input operand1. - OP2: Input operand2. - OP3: Input operand3 or NULL_RTX. - SUBTYPE: Describe the operation. */ - -void -fp16_vectorization (enum rtx_code icode, - rtx result, - rtx op1, - rtx op2, - rtx op3, - enum fp16_operation subtype) -{ - gcc_assert (can_create_pseudo_p ()); - - machine_mode result_mode = GET_MODE (result); - rtx op_orig[3] = { op1, op2, op3 }; - rtx op_hi[3]; - rtx op_lo[3]; - rtx result_hi; - rtx result_lo; - size_t n_opts; - - switch (subtype) - { - case FP16_BINARY: - n_opts = 2; - break; - - case FP16_FMA: - case FP16_FMS: - case FP16_NFMA: - case FP16_NFMS: - n_opts = 3; - break; - - default: - gcc_unreachable (); - } - - /* Allocate 2 temporaries for the results and the input operands. */ - result_hi = gen_reg_rtx (V4SFmode); - result_lo = gen_reg_rtx (V4SFmode); - - for (size_t i = 0; i < n_opts; i++) - { - gcc_assert (op_orig[i] != NULL_RTX); - op_hi[i] = gen_reg_rtx (V4SFmode); /* high register. */ - op_lo[i] = gen_reg_rtx (V4SFmode); /* low register. */ - - rtx interleave_hi = gen_reg_rtx (result_mode); - rtx interleave_lo = gen_reg_rtx (result_mode); - rtx orig = op_orig[i]; - - rs6000_expand_interleave (interleave_hi, orig, orig, !BYTES_BIG_ENDIAN); - rs6000_expand_interleave (interleave_lo, orig, orig, BYTES_BIG_ENDIAN); - - if (result_mode == V8HFmode) - { - emit_insn (gen_xvcvhpsp_v8hf (op_hi[i], interleave_hi)); - emit_insn (gen_xvcvhpsp_v8hf (op_lo[i], interleave_lo)); - } - - else if (result_mode == V8BFmode) - { - emit_insn (gen_xvcvbf16spn_v8bf (op_hi[i], interleave_hi)); - emit_insn (gen_xvcvbf16spn_v8bf (op_lo[i], interleave_lo)); - } - - else - gcc_unreachable (); - } - - /* Do 2 sets of V4SFmode operations. */ - switch (subtype) - { - case FP16_BINARY: - emit_insn (gen_rtx_SET (result_hi, - gen_rtx_fmt_ee (icode, V4SFmode, - op_hi[0], - op_hi[1]))); - - emit_insn (gen_rtx_SET (result_lo, - gen_rtx_fmt_ee (icode, V4SFmode, - op_lo[0], - op_lo[1]))); - break; - - case FP16_FMA: - case FP16_FMS: - case FP16_NFMA: - case FP16_NFMS: - { - rtx op1_hi = op_hi[0]; - rtx op2_hi = op_hi[1]; - rtx op3_hi = op_hi[2]; - - rtx op1_lo = op_lo[0]; - rtx op2_lo = op_lo[1]; - rtx op3_lo = op_lo[2]; - - if (subtype == FP16_FMS || subtype == FP16_NFMS) - { - op3_hi = gen_rtx_NEG (V4SFmode, op3_hi); - op3_lo = gen_rtx_NEG (V4SFmode, op3_lo); - } - - rtx op_fma_hi = gen_rtx_FMA (V4SFmode, op1_hi, op2_hi, op3_hi); - rtx op_fma_lo = gen_rtx_FMA (V4SFmode, op1_lo, op2_lo, op3_lo); - - if (subtype == FP16_NFMA || subtype == FP16_NFMS) - { - op_fma_hi = gen_rtx_NEG (V4SFmode, op_fma_hi); - op_fma_lo = gen_rtx_NEG (V4SFmode, op_fma_lo); - } - - emit_insn (gen_rtx_SET (result_hi, op_fma_hi)); - emit_insn (gen_rtx_SET (result_lo, op_fma_lo)); - } - break; - - default: - gcc_unreachable (); - } - - /* Combine the 2 V4SFmode operations into one V8HFmode/V8BFmode vector. */ - if (result_mode == V8HFmode) - emit_insn (gen_vec_pack_trunc_v4sf_v8hf (result, result_hi, result_lo)); - - else if (result_mode == V8BFmode) - emit_insn (gen_vec_pack_trunc_v4sf_v8bf (result, result_hi, result_lo)); - - else - gcc_unreachable (); - - return; -} - -/* Expand a bfloat16 scalar floating point operation: - - ICODE: Operation to perform. - RESULT: Result of the operation. - OP1: Input operand1. - OP2: Input operand2. - OP3: Input operand3 or NULL_RTX. - SUBTYPE: Describe the operation. - - The operation is done as a V4SFmode vector operation. This is because - converting BFmode from a scalar BFmode to SFmode to do the operation and - back again takes quite a bit of time. GCC will only generate the native - operation if -Ofast is used. The float16.md code that calls this function - adds various combine operations to do the operation in V4SFmode instead of - SFmode. */ - -void -bfloat16_operation_as_v4sf (enum rtx_code icode, - rtx result, - rtx op1, - rtx op2, - rtx op3, - enum fp16_operation subtype) -{ - gcc_assert (can_create_pseudo_p ()); - - rtx result_v4sf = gen_reg_rtx (V4SFmode); - rtx ops_orig[3] = { op1, op2, op3 }; - rtx ops_v4sf[3]; - size_t n_opts; - - switch (subtype) - { - case FP16_BINARY: - n_opts = 2; - gcc_assert (op3 == NULL_RTX); - break; - - case FP16_FMA: - case FP16_FMS: - case FP16_NFMA: - case FP16_NFMS: - gcc_assert (icode == FMA); - n_opts = 3; - break; - - default: - gcc_unreachable (); - } - - for (size_t i = 0; i < n_opts; i++) - { - rtx op = ops_orig[i]; - rtx tmp = ops_v4sf[i] = gen_reg_rtx (V4SFmode); - - gcc_assert (op != NULL_RTX); - - /* Remove truncation/extend added. */ - if (GET_CODE (op) == FLOAT_EXTEND || GET_CODE (op) == FLOAT_TRUNCATE) - op = XEXP (op, 0); - - /* Convert operands to V4SFmode format. We use SPLAT for registers to - get the value into the upper 32-bits. We can use XXSPLTW to splat - words instead of VSPLTIH since the XVCVBF16SPN instruction ignores the - odd half-words, and XXSPLTW can operate on all VSX registers instead - of just the Altivec registers. Using SPLAT instead of a shift also - insure that other bits are not a signalling NaN. If we are using - XXSPLTIW or XXSPLTIB to load the constant the other bits are - duplicated. */ - - if (op == CONST0_RTX (SFmode) || op == CONST0_RTX (BFmode)) - emit_move_insn (tmp, CONST0_RTX (V4SFmode)); - - else if (GET_MODE (op) == BFmode) - { - emit_insn (gen_xxspltw_bf (tmp, force_reg (BFmode, op))); - emit_insn (gen_xvcvbf16spn_bf (tmp, tmp)); - } - - else if (GET_MODE (op) == SFmode) - { - if (GET_CODE (op) == CONST_DOUBLE) - { - rtvec v = rtvec_alloc (4); - - for (size_t i = 0; i < 4; i++) - RTVEC_ELT (v, i) = op; - - emit_insn (gen_rtx_SET (tmp, - gen_rtx_CONST_VECTOR (V4SFmode, v))); - } - - else - emit_insn (gen_vsx_splat_v4sf (tmp, - force_reg (SFmode, op))); - } - - else - gcc_unreachable (); - } - - /* Do the operation in V4SFmode. */ - switch (subtype) - { - case FP16_BINARY: - emit_insn (gen_rtx_SET (result_v4sf, - gen_rtx_fmt_ee (icode, V4SFmode, - ops_v4sf[0], - ops_v4sf[1]))); - break; - - case FP16_FMA: - case FP16_FMS: - case FP16_NFMA: - case FP16_NFMS: - { - rtx op1 = ops_v4sf[0]; - rtx op2 = ops_v4sf[1]; - rtx op3 = ops_v4sf[2]; - - if (subtype == FP16_FMS || subtype == FP16_NFMS) - op3 = gen_rtx_NEG (V4SFmode, op3); - - rtx op_fma = gen_rtx_FMA (V4SFmode, op1, op2, op3); - - if (subtype == FP16_NFMA || subtype == FP16_NFMS) - op_fma = gen_rtx_NEG (V4SFmode, op_fma); - - emit_insn (gen_rtx_SET (result_v4sf, op_fma)); - } - break; - - default: - gcc_unreachable (); - } - - /* Convert V4SF result back to scalar mode. */ - if (GET_MODE (result) == BFmode) - emit_insn (gen_xvcvspbf16_bf (result, result_v4sf)); - - else if (GET_MODE (result) == SFmode) - { - rtx element = GEN_INT (WORDS_BIG_ENDIAN ? 2 : 3); - emit_insn (gen_vsx_extract_v4sf (result, result_v4sf, element)); - } - - else - gcc_unreachable (); -} diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md deleted file mode 100644 index 7fafaddaf5bc..000000000000 --- a/gcc/config/rs6000/float16.md +++ /dev/null @@ -1,1263 +0,0 @@ -;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler -;; Copyright (C) 1990-2025 Free Software Foundation, Inc. -;; Contributed by Richard Kenner ([email protected]) - -;; This file is part of GCC. - -;; GCC is free software; you can redistribute it and/or modify it -;; under the terms of the GNU General Public License as published -;; by the Free Software Foundation; either version 3, or (at your -;; option) any later version. - -;; GCC is distributed in the hope that it will be useful, but WITHOUT -;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public -;; License for more details. - -;; You should have received a copy of the GNU General Public License -;; along with GCC; see the file COPYING3. If not see -;; <http://www.gnu.org/licenses/>. - -;; Support for _Float16 (HFmode) and __bfloat16 (BFmode) - -;; Mode iterator for 16-bit floating point modes both as a scalar and -;; as a vector. -(define_mode_iterator FP16 [(BF "TARGET_BFLOAT16") - (HF "TARGET_FLOAT16")]) - -(define_mode_iterator VFP16 [(V8BF "TARGET_BFLOAT16") - (V8HF "TARGET_FLOAT16")]) - -;; Mode iterator for 16-bit floating point modes on machines with -;; hardware support both as a scalar and as a vector. -(define_mode_iterator FP16_HW [(BF "TARGET_BFLOAT16_HW") - (HF "TARGET_FLOAT16_HW")]) - -(define_mode_iterator VFP16_HW [(V8BF "TARGET_BFLOAT16_HW") - (V8HF "TARGET_FLOAT16_HW")]) - -;; Mode iterator for floating point modes other than SF/DFmode that we -;; convert to/from _Float16 (HFmode) via DFmode. -(define_mode_iterator fp16_float_convert [TF KF IF SD DD TD]) - -;; Mode attribute giving the instruction to convert the even -;; V8HFmode or V8BFmode elements to V4SFmode -(define_mode_attr cvt_fp16_to_v4sf_insn [(BF "xvcvbf16spn") - (HF "xvcvhpsp") - (V8BF "xvcvbf16spn") - (V8HF "xvcvhpsp")]) - -;; Mode attribute giving the vector mode for a 16-bit floating point -;; scalar in both upper and lower case. -(define_mode_attr FP16_VECTOR8 [(BF "V8BF") - (HF "V8HF")]) - -(define_mode_attr fp16_vector8 [(BF "v8bf") - (HF "v8hf")]) - -;; Mode attribute giving the vector mode with 4 16-bit floating point -;; elements given a scalar or 8 element vector. -(define_mode_attr FP16_VECTOR4 [(BF "V4BF") - (HF "V4HF") - (V8BF "V4BF") - (V8HF "V4HF")]) - -;; Binary operators for bfloat16/float16 vectorization. -(define_code_iterator FP16_BINARY_OP [plus minus mult smax smin]) - -;; Standard names for the unary/binary/ternary operators -(define_code_attr fp16_names [(abs "abs") - (fma "fma") - (plus "add") - (minus "sub") - (mult "mul") - (neg "neg") - (smax "smax") - (smin "smin")]) - -;; UNSPEC constants -(define_c_enum "unspec" - [UNSPEC_FP16_SHIFT_LEFT_32BIT - UNSPEC_CVT_FP16_TO_V4SF - UNSPEC_XXSPLTW_FP16 - UNSPEC_XVCVSPBF16_BF - UNSPEC_XVCVSPHP_V8HF - UNSPEC_XVCVSPBF16_V8BF]) - -;; _Float16 and __bfloat16 moves -(define_expand "mov<mode>" - [(set (match_operand:FP16 0 "nonimmediate_operand") - (match_operand:FP16 1 "any_operand"))] - "" -{ - if (MEM_P (operands[0]) && !REG_P (operands[1])) - operands[1] = force_reg (<MODE>mode, operands[1]); -}) - -;; On power10, we can load up HFmode and BFmode constants with xxspltiw -;; or pli. -(define_insn "*mov<mode>_xxspltiw" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,wa,?r,?r") - (match_operand:FP16 1 "fp16_xxspltiw_constant" "j,eP,j,eP"))] - "TARGET_PREFIXED || operands[1] == CONST0_RTX (<MODE>mode)" -{ - rtx op1 = operands[1]; - const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op1); - long real_words[1]; - - if (op1 == CONST0_RTX (<MODE>mode)) - return (!vsx_register_operand (operands[0], <MODE>mode) - ? "li %0,0" - : "xxlxor %x0,%x0,%x0"); - - real_to_target (real_words, rtype, <MODE>mode); - operands[2] = GEN_INT (real_words[0]); - return (vsx_register_operand (operands[0], <MODE>mode) - ? "xxspltiw %x0,%2" - : "pli %0,%2"); -} - [(set_attr "type" "veclogical, vecsimple, *, *") - (set_attr "prefixed" "no, yes, no, yes")]) - -(define_insn "*mov<mode>_internal" - [(set (match_operand:FP16 0 "nonimmediate_operand" - "=wa, wa, Z, r, r, - m, r, wa, wa, r") - - (match_operand:FP16 1 "any_operand" - "wa, Z, wa, r, m, - r, wa, r, j, j"))] - "gpc_reg_operand (operands[0], <MODE>mode) - || gpc_reg_operand (operands[1], <MODE>mode)" - "@ - xxlor %x0,%x1,%x1 - lxsihzx %x0,%y1 - stxsihx %x1,%y0 - mr %0,%1 - lhz%U1%X1 %0,%1 - sth%U0%X0 %1,%0 - mfvsrwz %0,%x1 - mtvsrwz %x0,%1 - xxlxor %x0,%x0,%x0 - li %0,0" - [(set_attr "type" "vecsimple, fpload, fpstore, *, load, - store, mtvsr, mfvsr, veclogical, *") - (set_attr "isa" "*, p9v, p9v, *, *, - *, p8v, p8v, p9v, *")]) - -;; Vector duplicate -(define_insn "*vecdup<mode>_reg" - [(set (match_operand:<FP16_VECTOR8> 0 "altivec_register_operand" "=v") - (vec_duplicate:<FP16_VECTOR8> - (match_operand:FP16 1 "altivec_register_operand" "v")))] - "" - "vsplth %0,%1,3" - [(set_attr "type" "vecperm")]) - -(define_insn "*vecdup<mode>_const" - [(set (match_operand:<FP16_VECTOR8> 0 "vsx_register_operand" "=wa,wa") - (vec_duplicate:<FP16_VECTOR8> - (match_operand:FP16 1 "fp16_xxspltiw_constant" "j,eP")))] - "TARGET_PREFIXED || operands[1] == CONST0_RTX (<MODE>mode)" -{ - rtx op1 = operands[1]; - if (op1 == CONST0_RTX (<MODE>mode)) - return "xxlxor %x0,%x0,%x0"; - - const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op1); - long real_words[1]; - - real_to_target (real_words, rtype, <MODE>mode); - operands[2] = GEN_INT (real_words[0]); - return "xxspltiw %x0,2"; -} - [(set_attr "type" "veclogical,vecperm") - (set_attr "prefixed" "*,yes")]) - -;; Convert IEEE 16-bit floating point to/from other floating point modes. - -(define_insn "extendhf<mode>2" - [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa") - (float_extend:SFDF - (match_operand:HF 1 "vsx_register_operand" "wa")))] - "TARGET_FLOAT16_HW" - "xscvhpdp %x0,%x1" - [(set_attr "type" "fpsimple")]) - -(define_insn "trunc<mode>hf2" - [(set (match_operand:HF 0 "vsx_register_operand" "=wa") - (float_truncate:HF - (match_operand:SFDF 1 "vsx_register_operand" "wa")))] - "TARGET_FLOAT16_HW" - "xscvdphp %x0,%x1" - [(set_attr "type" "fpsimple")]) - -;; Convert BFmode to SFmode/DFmode. -;; 3 instructions are generated: -;; VSPLTH -- duplicate BFmode into all elements -;; XVCVBF16SPN -- convert even BFmode elements to SFmode -;; XSCVSPNDP -- convert memory format of SFmode to DFmode. -(define_insn_and_split "extendbf<mode>2" - [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa") - (float_extend:SFDF - (match_operand:BF 1 "vsx_register_operand" "v"))) - (clobber (match_scratch:V8BF 2 "=v"))] - "TARGET_BFLOAT16_HW" - "#" - "&& 1" - [(pc)] -{ - rtx op0 = operands[0]; - rtx op1 = operands[1]; - rtx op2_v8bf = operands[2]; - - if (GET_CODE (op2_v8bf) == SCRATCH) - op2_v8bf = gen_reg_rtx (V8BFmode); - - rtx op2_v4sf = gen_lowpart (V4SFmode, op2_v8bf); - - /* XXSLDWI -- shift BFmode element into the upper 32 bits. */ - emit_insn (gen_v8bf_shift_left_32bit (op2_v8bf, op1)); - - /* XVCVBF16SPN -- convert even V8BFmode elements to V4SFmode. */ - emit_insn (gen_cvt_fp16_to_v4sf_v8bf (op2_v4sf, op2_v8bf)); - - /* XSCVSPNDP -- convert single V4SFmode element to DFmode. */ - emit_insn (GET_MODE (op0) == SFmode - ? gen_xscvspdpn_sf (op0, op2_v4sf) - : gen_vsx_xscvspdpn (op0, op2_v4sf)); - - DONE; -} - [(set_attr "type" "fpsimple") - (set_attr "length" "12")]) - -;; Convert a SFmode scalar represented as DFmode to elements 0 and 1 of -;; V4SFmode. -(define_insn "xscvdpspn_sf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVSPDP))] - "VECTOR_UNIT_VSX_P (SFmode)" - "xscvdpspn %x0,%x1" - [(set_attr "type" "fp")]) - -;; Convert element 0 of a V4SFmode to scalar SFmode (which on the -;; PowerPC uses the DFmode encoding). -(define_insn "xscvspdpn_sf" - [(set (match_operand:SF 0 "vsx_register_operand" "=wa") - (unspec:SF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVSPDPN))] - "TARGET_XSCVSPDPN" - "xscvspdpn %x0,%x1" - [(set_attr "type" "fp")]) - -;; Vector shift left by 32 bits to get the 16-bit floating point value -;; into the upper 32 bits for the conversion. -(define_insn "<fp16_vector8>_shift_left_32bit" - [(set (match_operand:<FP16_VECTOR8> 0 "vsx_register_operand" "=wa") - (unspec:<FP16_VECTOR8> - [(match_operand:FP16_HW 1 "vsx_register_operand" "wa")] - UNSPEC_FP16_SHIFT_LEFT_32BIT))] - "" - "xxsldwi %x0,%x1,%x1,1" - [(set_attr "type" "vecperm")]) - -;; Convert SFmode/DFmode to BFmode. -;; 2 instructions are generated: -;; XSCVDPSPN -- convert SFmode/DFmode scalar to V4SFmode -;; XVCVSPBF16 -- convert V4SFmode to even V8BFmode - -(define_insn_and_split "trunc<mode>bf2" - [(set (match_operand:BF 0 "vsx_register_operand" "=wa") - (float_truncate:BF - (match_operand:SFDF 1 "vsx_register_operand" "wa"))) - (clobber (match_scratch:V4SF 2 "=wa"))] - "TARGET_BFLOAT16_HW" - "#" - "&& 1" - [(pc)] -{ - rtx op0 = operands[0]; - rtx op1 = operands[1]; - rtx op2 = operands[2]; - - if (GET_CODE (op2) == SCRATCH) - op2 = gen_reg_rtx (V4SFmode); - - emit_insn (GET_MODE (op1) == SFmode - ? gen_xscvdpspn_sf (op2, op1) - : gen_vsx_xscvdpspn (op2, op1)); - - emit_insn (gen_xvcvspbf16_bf (op0, op2)); - DONE; -} - [(set_attr "type" "fpsimple")]) - -(define_insn "vsx_xscvdpspn_sf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVDPSPN))] - "TARGET_XSCVDPSPN" - "xscvdpspn %x0,%x1" - [(set_attr "type" "fp")]) - -;; Convert the even elements of a vector 16-bit floating point to -;; V4SFmode. Deal with little endian vs. big endian element ordering -;; in identifying which elements are converted. - -(define_expand "cvt_fp16_to_v4sf_<mode>" - [(set (match_operand:V4SF 0 "vsx_register_operand") - (float_extend:V4SF - (vec_select:<FP16_VECTOR4> - (match_operand:VFP16_HW 1 "vsx_register_operand") - (parallel [(match_dup 2) - (match_dup 3) - (match_dup 4) - (match_dup 5)]))))] - "" -{ - int endian_adjust = WORDS_BIG_ENDIAN ? 0 : 1; - operands[2] = GEN_INT (0 + endian_adjust); - operands[3] = GEN_INT (2 + endian_adjust); - operands[4] = GEN_INT (4 + endian_adjust); - operands[5] = GEN_INT (6 + endian_adjust); -}) - -(define_insn "*cvt_fp16_to_v4sf_<mode>_le" - [(set (match_operand:V4SF 0 "vsx_register_operand") - (float_extend:V4SF - (vec_select:<FP16_VECTOR4> - (match_operand:VFP16_HW 1 "vsx_register_operand") - (parallel [(const_int 1) - (const_int 3) - (const_int 5) - (const_int 7)]))))] - "!WORDS_BIG_ENDIAN" - "<cvt_fp16_to_v4sf_insn> %x0,%x1" - [(set_attr "type" "vecfloat")]) - -(define_insn "*cvt_fp16_to_v4sf_<mode>_be" - [(set (match_operand:V4SF 0 "vsx_register_operand") - (float_extend:V4SF - (vec_select:<FP16_VECTOR4> - (match_operand:VFP16_HW 1 "vsx_register_operand") - (parallel [(const_int 0) - (const_int 2) - (const_int 4) - (const_int 6)]))))] - "WORDS_BIG_ENDIAN" - "<cvt_fp16_to_v4sf_insn> %x0,%x1" - [(set_attr "type" "vecfloat")]) - -;; Duplicate and convert a 16-bit floating point scalar to V4SFmode. - -(define_insn_and_split "*dup_<mode>_to_v4sf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (vec_duplicate:V4SF - (float_extend:SF - (match_operand:FP16_HW 1 "vsx_register_operand" "wa"))))] - "" - "#" - "&& 1" - [(pc)] -{ - rtx op0 = operands[0]; - rtx op1 = operands[1]; - rtx op0_vfp16 = gen_lowpart (<FP16_VECTOR8>mode, op0); - - emit_insn (gen_xxspltw_<mode> (op0, op1)); - emit_insn (gen_cvt_fp16_to_v4sf_<fp16_vector8> (op0, op0_vfp16)); - DONE; -} - [(set_attr "length" "8") - (set_attr "type" "vecperm")]) - -;; Duplicate a HF/BF value so it can be used for xvcvhpspn/xvcvbf16spn. -;; Because xvcvhpspn/xvcvbf16spn only uses the even elements, we can -;; use xxspltw instead of vspltw. This has the advantage that the -;; register allocator can use any of the 64 VSX registers instead of -;; being limited to the 32 Altivec registers that VSPLTH would require. - -(define_insn "xxspltw_<mode>" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:FP16_HW 1 "vsx_register_operand" "wa")] - UNSPEC_XXSPLTW_FP16))] - "" - "xxspltw %x0,%x1,1" - [(set_attr "type" "vecperm")]) - -;; Convert a bfloat16 floating point scalar that has been splatted to -;; V4SFmode. - -(define_insn "xvcvbf16spn_bf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_CVT_FP16_TO_V4SF))] - "TARGET_BFLOAT16_HW" - "xvcvbf16spn %x0,%x1" - [(set_attr "type" "vecperm")]) - -;; Convert a V4SFmode vector to a 16-bit floating point scalar. We -;; only care about the 2nd V4SFmode element, which is the element we -;; converted the 16-bit scalar (4th element) to V4SFmode to do the -;; operation, and converted it back. - -(define_insn "xvcvspbf16_bf" - [(set (match_operand:BF 0 "vsx_register_operand" "=wa") - (unspec:BF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_XVCVSPBF16_BF))] - "TARGET_BFLOAT16_HW" - "xvcvspbf16 %x0,%x1" - [(set_attr "type" "vecfloat")]) - -;; Convert between HFmode/BFmode and 128-bit binary floating point and -;; decimal floating point types. We use convert_move since some of the -;; types might not have valid RTX expanders. We use DFmode as the -;; intermediate conversion destination. - -(define_expand "extend<FP16_HW:mode><fp16_float_convert:mode>2" - [(set (match_operand:fp16_float_convert 0 "vsx_register_operand") - (float_extend:fp16_float_convert - (match_operand:FP16_HW 1 "vsx_register_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - emit_insn (gen_extend<FP16_HW:mode>df2 (df_tmp, operands[1])); - convert_move (operands[0], df_tmp, 0); - DONE; -}) - -(define_expand "trunc<fp16_float_convert:mode><FP16_HW:mode>2" - [(set (match_operand:FP16_HW 0 "vsx_register_operand") - (float_truncate:FP16_HW - (match_operand:fp16_float_convert 1 "vsx_register_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - - convert_move (df_tmp, operands[1], 0); - emit_insn (gen_truncdf<FP16_HW:mode>2 (operands[0], df_tmp)); - DONE; -}) - -;; Convert integers to 16-bit floating point modes. -(define_expand "float<GPR:mode><FP16_HW:mode>2" - [(set (match_operand:FP16_HW 0 "vsx_register_operand") - (float:FP16_HW - (match_operand:GPR 1 "nonimmediate_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - emit_insn (gen_float<GPR:mode>df2 (df_tmp, operands[1])); - emit_insn (gen_truncdf<FP16_HW:mode>2 (operands[0], df_tmp)); - DONE; -}) - -(define_expand "floatuns<GPR:mode><FP16_HW:mode>2" - [(set (match_operand:FP16_HW 0 "vsx_register_operand") - (unsigned_float:FP16_HW - (match_operand:GPR 1 "nonimmediate_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - emit_insn (gen_floatuns<GPR:mode>df2 (df_tmp, operands[1])); - emit_insn (gen_truncdf<FP16_HW:mode>2 (operands[0], df_tmp)); - DONE; -}) - -;; Convert 16-bit floating point modes to integers -(define_expand "fix_trunc<FP16_HW:mode><GPR:mode>2" - [(set (match_operand:GPR 0 "vsx_register_operand") - (fix:GPR - (match_operand:FP16_HW 1 "vsx_register_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - emit_insn (gen_extend<FP16_HW:mode>df2 (df_tmp, operands[1])); - emit_insn (gen_fix_truncdf<GPR:mode>2 (operands[0], df_tmp)); - DONE; -}) - -(define_expand "fixuns_trunc<FP16_HW:mode><GPR:mode>2" - [(set (match_operand:GPR 0 "vsx_register_operand") - (unsigned_fix:GPR - (match_operand:FP16_HW 1 "vsx_register_operand")))] - "" -{ - rtx df_tmp = gen_reg_rtx (DFmode); - emit_insn (gen_extend<FP16_HW:mode>df2 (df_tmp, operands[1])); - emit_insn (gen_fixuns_truncdf<GPR:mode>2 (operands[0], df_tmp)); - DONE; -}) - -;; Negate 16-bit floating point by XOR with -0.0. - -(define_insn_and_split "neg<mode>2" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr") - (neg:FP16 (match_operand:FP16 1 "gpc_reg_operand" "wa,wr"))) - (clobber (match_scratch:FP16 2 "=&wa,&r"))] - "" - "#" - "&& 1" - [(set (match_dup 2) - (match_dup 3)) - (set (match_dup 0) - (xor:FP16 (match_dup 1) - (match_dup 2)))] -{ - if (GET_CODE (operands[2]) == SCRATCH) - operands[2] = gen_reg_rtx (<MODE>mode); - - REAL_VALUE_TYPE dconst; - - gcc_assert (real_from_string (&dconst, "-0.0") == 0); - - rtx rc = const_double_from_real_value (dconst, <MODE>mode); - if (!TARGET_PREFIXED) - rc = force_const_mem (<MODE>mode, rc); - - operands[3] = rc; -} - [(set_attr "type" "veclogical,integer") - (set_attr "length" "16")]) - -;; 16-bit floating point absolute value - -(define_insn_and_split "abs<mode>2" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr") - (abs:FP16 - (match_operand:FP16 1 "gpc_reg_operand" "wa,wr"))) - (clobber (match_scratch:FP16 2 "=&wa,&r"))] - "" - "#" - "&& 1" - [(set (match_dup 2) - (match_dup 3)) - (set (match_dup 0) - (and:FP16 (match_dup 1) - (not:FP16 (match_dup 2))))] -{ - if (GET_CODE (operands[2]) == SCRATCH) - operands[2] = gen_reg_rtx (<MODE>mode); - - REAL_VALUE_TYPE dconst; - - gcc_assert (real_from_string (&dconst, "-0.0") == 0); - - rtx rc = const_double_from_real_value (dconst, <MODE>mode); - - if (!TARGET_PREFIXED) - rc = force_const_mem (<MODE>mode, rc); - - operands[3] = rc; -} - [(set_attr "type" "veclogical,integer") - (set_attr "length" "16")]) - -;; 16-bit negative floating point absolute value - -(define_insn_and_split "*nabs<mode>2" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,?wr") - (neg:FP16 - (abs:FP16 - (match_operand:FP16 1 "gpc_reg_operand" "wa,wr")))) - (clobber (match_scratch:FP16 2 "=&wa,&r"))] - "" - "#" - "&& 1" - [(set (match_dup 2) - (match_dup 3)) - (set (match_dup 0) - (ior:FP16 (match_dup 1) - (match_dup 2)))] -{ - if (GET_CODE (operands[2]) == SCRATCH) - operands[2] = gen_reg_rtx (<MODE>mode); - - REAL_VALUE_TYPE dconst; - - gcc_assert (real_from_string (&dconst, "-0.0") == 0); - rtx rc = const_double_from_real_value (dconst, <MODE>mode); - - if (!TARGET_PREFIXED) - rc = force_const_mem (<MODE>mode, rc); - - operands[3] = rc; -} - [(set_attr "type" "veclogical,integer") - (set_attr "length" "16")]) - -;; Add logical operations for 16-bit floating point types that are used -;; for things like negate, abs, and negative abs. Possibly in the -;; future we might need logical operators for extracting exponents and -;; mantissas. -(define_expand "and<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (and:FP16 (match_operand:FP16 1 "gpc_reg_operand") - (match_operand:FP16 2 "gpc_reg_operand")))] - "" - "") - -(define_expand "ior<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (ior:FP16 (match_operand:FP16 1 "gpc_reg_operand") - (match_operand:FP16 2 "gpc_reg_operand")))] - "" - "") - -(define_expand "xor<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (xor:FP16 (match_operand:FP16 1 "gpc_reg_operand") - (match_operand:FP16 2 "gpc_reg_operand")))] - "" - "") - -(define_expand "nor<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (and:FP16 - (not:FP16 (match_operand:FP16 1 "gpc_reg_operand")) - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand"))))] - "" - "") - -(define_expand "andn<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (and:FP16 - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand")) - (match_operand:FP16 1 "gpc_reg_operand")))] - "" - "") - -(define_expand "eqv<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (not:FP16 - (xor:FP16 (match_operand:FP16 1 "gpc_reg_operand") - (match_operand:FP16 2 "gpc_reg_operand"))))] - "" - "") - -;; Rewrite nand into canonical form -(define_expand "nand<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (ior:FP16 - (not:FP16 (match_operand:FP16 1 "gpc_reg_operand")) - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand"))))] - "" - "") - -;; The canonical form is to have the negated element first, so we need to -;; reverse arguments. -(define_expand "iorn<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand") - (ior:FP16 - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand")) - (match_operand:FP16 1 "gpc_reg_operand")))] - "" - "") - -;; AND, IOR, and XOR insns. Unlike HImode operations prefer using -;; floating point/vector registers over GPRs. -(define_insn "*bool<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,r") - (match_operator:FP16 3 "boolean_operator" - [(match_operand:FP16 1 "gpc_reg_operand" "wa,r") - (match_operand:FP16 2 "gpc_reg_operand" "wa,r")]))] - "" - "@ - xxl%q3 %x0,%x1,%x2 - %q3 %0,%1,%2" - [(set_attr "type" "veclogical,logical")]) - -;; ANDC, IORC, and EQV insns. -(define_insn "*boolc<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,r") - (match_operator:FP16 3 "boolean_operator" - [(not:FP16 (match_operand:FP16 2 "gpc_reg_operand" "wa,r")) - (match_operand:FP16 1 "gpc_reg_operand" "wa,r")]))] - "" - "@ - xxl%q3 %x0,%x1,%x2 - %q3 %0,%1,%2" - [(set_attr "type" "veclogical,logical")]) - -(define_insn "*boolc<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,r") - (match_operator:FP16 3 "boolean_operator" - [(match_operand:FP16 1 "gpc_reg_operand" "wa,r") - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand" "wa,r"))]))] - "" - "@ - xxl%q3 %x0,%x1,%x2 - %q3 %0,%1,%2" - [(set_attr "type" "veclogical,logical")]) - -;; NOR and NAND insns. -(define_insn "*boolcc<mode>3" - [(set (match_operand:FP16 0 "gpc_reg_operand" "=wa,r") - (match_operator:FP16 3 "boolean_operator" - [(not:FP16 (match_operand:FP16 1 "gpc_reg_operand" "wa,r")) - (not:FP16 (match_operand:FP16 2 "gpc_reg_operand" "wa,r"))]))] - "" - "@ - xxl%q3 %x0,%x1,%x2 - %q3 %0,%1,%2" - [(set_attr "type" "veclogical,logical")]) - -;; Optimize __bfloat16 binary operations. Unlike _Float16 where we -;; have instructions to convert between HFmode and SFmode as scalar -;; values, with BFmode, we only have vector conversions. Thus to do: -;; -;; __bfloat16 a, b, c; -;; a = b + c; -;; -;; the GCC compiler would normally generate: -;; -;; lxsihzx 0,4,2 // load __bfloat16 value b -;; lxsihzx 12,5,2 // load __bfloat16 value c -;; xxsldwi 0,0,0,1 // shift b into bits 16..31 -;; xxsldwi 12,12,12,1 // shift c into bits 16..31 -;; xvcvbf16spn 0,0 // vector convert b into V4SFmode -;; xvcvbf16spn 12,12 // vector convert c into V4SFmode -;; xscvspdpn 0,0 // convert b into SFmode scalar -;; xscvspdpn 12,12 // convert c into SFmode scalar -;; fadds 0,0,12 // add b+c -;; xscvdpspn 0,0 // convert b+c into SFmode memory format -;; xvcvspbf16 0,0 // convert b+c into BFmode memory format -;; stxsihx 0,3,2 // store b+c -;; -;; Using the following combiner patterns, the code generated would now -;; be: -;; -;; lxsihzx 12,4,2 // load __bfloat16 value b -;; lxsihzx 0,5,2 // load __bfloat16 value c -;; xxspltw 12,12,1 // shift b into bits 16..31 -;; xxspltw 0,0,1 // shift c into bits 16..31 -;; xvcvbf16spn 12,12 // vector convert b into V4SFmode -;; xvcvbf16spn 0,0 // vector convert c into V4SFmode -;; xvaddsp 0,0,12 // vector b+c in V4SFmode -;; xvcvspbf16 0,0 // convert b+c into BFmode memory format -;; stxsihx 0,3,2 // store b+c -;; -;; We cannot just define insns like 'addbf3' to keep the operation as -;; BFmode because GCC will not generate these patterns unless the user -;; uses -Ofast. Without -Ofast, it will always convert BFmode into -;; SFmode. - -(define_insn_and_split "*bfloat16_binary_op_internal1" - [(set (match_operand:SF 0 "vsx_register_operand") - (match_operator:SF 1 "fp16_binary_operator" - [(match_operand:SF 2 "bfloat16_v4sf_operand") - (match_operand:SF 3 "bfloat16_v4sf_operand")]))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[2], SFmode) - || bfloat16_bf_operand (operands[3], SFmode))" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (GET_CODE (operands[1]), operands[0], operands[2], - operands[3], NULL_RTX, FP16_BINARY); - DONE; -}) - -(define_insn_and_split "*bfloat16_binary_op_internal2" - [(set (match_operand:BF 0 "vsx_register_operand") - (float_truncate:BF - (match_operator:SF 1 "fp16_binary_operator" - [(match_operand:SF 2 "bfloat16_v4sf_operand") - (match_operand:SF 3 "bfloat16_v4sf_operand")])))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[2], SFmode) - || bfloat16_bf_operand (operands[3], SFmode))" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (GET_CODE (operands[1]), operands[0], operands[2], - operands[3], NULL_RTX, FP16_BINARY); - DONE; -}) - -(define_insn_and_split "*bfloat16_fma_internal1" - [(set (match_operand:SF 0 "vsx_register_operand") - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (match_operand:SF 3 "bfloat16_v4sf_operand")))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_FMA); - DONE; -}) - -(define_insn_and_split "*bfloat16_fma_internal2" - [(set (match_operand:BF 0 "vsx_register_operand" "=wa") - (float_truncate:BF - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (match_operand:SF 3 "bfloat16_v4sf_operand"))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_FMA); - DONE; -}) - -(define_insn_and_split "*bfloat16_fms_internal1" - [(set (match_operand:SF 0 "vsx_register_operand") - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (neg:SF - (match_operand:SF 3 "bfloat16_v4sf_operand"))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_FMS); - DONE; -}) - -(define_insn_and_split "*bfloat16_fms_internal2" - [(set (match_operand:BF 0 "vsx_register_operand") - (float_truncate:BF - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (neg:SF - (match_operand:SF 3 "bfloat16_v4sf_operand")))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_FMS); - DONE; -}) - -(define_insn_and_split "*bfloat16_nfma_internal1" - [(set (match_operand:SF 0 "vsx_register_operand") - (neg:SF - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (match_operand:SF 3 "bfloat16_v4sf_operand"))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMA); - DONE; -}) - -(define_insn_and_split "*bfloat16_nfma_internal2" - [(set (match_operand:BF 0 "vsx_register_operand" "=wa") - (float_truncate:BF - (neg:SF - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (match_operand:SF 3 "bfloat16_v4sf_operand")))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMA); - DONE; -}) - -(define_insn_and_split "*bfloat16_nfma_internal3" - [(set (match_operand:BF 0 "vsx_register_operand" "=wa") - (neg:BF - (float_truncate:BF - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (match_operand:SF 3 "bfloat16_v4sf_operand")))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMA); - DONE; -}) - -(define_insn_and_split "*bfloat16_nfms_internal1" - [(set (match_operand:SF 0 "vsx_register_operand") - (neg:SF - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (neg:SF - (match_operand:SF 3 "bfloat16_v4sf_operand")))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMS); - DONE; -}) - -(define_insn_and_split "*bfloat16_nfms_internal2" - [(set (match_operand:BF 0 "vsx_register_operand") - (float_truncate:BF - (neg:SF - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (neg:SF - (match_operand:SF 3 "bfloat16_v4sf_operand"))))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMS); - DONE; -}) - -(define_insn_and_split "*bfloat16_nfms_internal3" - [(set (match_operand:BF 0 "vsx_register_operand") - (neg:BF - (float_truncate:BF - (fma:SF - (match_operand:SF 1 "bfloat16_v4sf_operand") - (match_operand:SF 2 "bfloat16_v4sf_operand") - (neg:SF - (match_operand:SF 3 "bfloat16_v4sf_operand"))))))] - "TARGET_BFLOAT16_HW && can_create_pseudo_p () - && (bfloat16_bf_operand (operands[1], SFmode) - + bfloat16_bf_operand (operands[2], SFmode) - + bfloat16_bf_operand (operands[3], SFmode) >= 2)" - "#" - "&& 1" - [(pc)] -{ - bfloat16_operation_as_v4sf (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMS); - DONE; -}) - -;; Add vectorization support for 16-bit floating point. - -;; Binary operators being vectorized. -(define_insn_and_split "<fp16_names><mode>3" - [(set (match_operand:VFP16_HW 0 "vsx_register_operand") - (FP16_BINARY_OP:VFP16_HW - (match_operand:VFP16_HW 1 "vsx_register_operand") - (match_operand:VFP16_HW 2 "vsx_register_operand")))] - "can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - fp16_vectorization (<CODE>, operands[0], operands[1], operands[2], NULL_RTX, - FP16_BINARY); - DONE; -}) - -;; FMA operations being vectorized. -(define_insn_and_split "fma<mode>4" - [(set (match_operand:VFP16_HW 0 "vsx_register_operand") - (fma:VFP16_HW - (match_operand:VFP16_HW 1 "vsx_register_operand") - (match_operand:VFP16_HW 2 "vsx_register_operand") - (match_operand:VFP16_HW 3 "vsx_register_operand")))] - "can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - fp16_vectorization (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_FMA); - DONE; -}) - -(define_insn_and_split "*fms<mode>4" - [(set (match_operand:VFP16_HW 0 "vsx_register_operand") - (fma:VFP16_HW - (match_operand:VFP16_HW 1 "vsx_register_operand") - (match_operand:VFP16_HW 2 "vsx_register_operand") - (neg:VFP16_HW - (match_operand:VFP16_HW 3 "vsx_register_operand"))))] - "can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - fp16_vectorization (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_FMS); - DONE; -}) - -(define_insn_and_split "*nfma<mode>4" - [(set (match_operand:VFP16_HW 0 "vsx_register_operand") - (neg:VFP16_HW - (fma:VFP16_HW - (match_operand:VFP16_HW 1 "vsx_register_operand") - (match_operand:VFP16_HW 2 "vsx_register_operand") - (match_operand:VFP16_HW 3 "vsx_register_operand"))))] - "can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - fp16_vectorization (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMA); - DONE; -}) - -(define_insn_and_split "*nfms<mode>4" - [(set (match_operand:VFP16_HW 0 "vsx_register_operand") - (neg:VFP16_HW - (fma:VFP16_HW - (match_operand:VFP16_HW 1 "vsx_register_operand") - (match_operand:VFP16_HW 2 "vsx_register_operand") - (neg:VFP16_HW - (match_operand:VFP16_HW 3 "vsx_register_operand")))))] - "can_create_pseudo_p ()" - "#" - "&& 1" - [(pc)] -{ - fp16_vectorization (FMA, operands[0], operands[1], operands[2], - operands[3], FP16_NFMS); - DONE; -}) - -;; If we do multiple __bfloat16 operations, between the first and -;; second operation, GCC will want to convert the first operation from -;; V4SFmode to SFmode and then reconvert it back to V4SFmode. On the -;; PowerPC, this is complicated because internally in the vector -;; register, SFmode values are stored as DFmode values. -;; -;; For example, if we have: -;; -;; __bfloat16 a, b, c, d; -;; a = b + c + d; -;; -;; We would generate: -;; -;; lxsihzx 0,4,2 // load b as BFmode -;; lxsihzx 11,5,2 // load c as BFmode -;; lxsihzx 12,6,2 // load d as BFmode -;; xxspltw 0,0,1 // shift b into bits 16..31 -;; xxspltw 11,11,1 // shift c into bits 16..31 -;; xxspltw 12,12,1 // shift d into bits 16..31 -;; xvcvbf16spn 0,0 // convert b into V4SFmode -;; xvcvbf16spn 11,11 // convert c into V4SFmode -;; xvcvbf16spn 12,12 // convert d into V4SFmode -;; xvaddsp 0,0,11 // calculate b+c as V4SFmode -;; xscvspdp 0,0 // convert b+c into DFmode memory format -;; xscvdpspn 0,0 // convert b+c into SFmode memory format -;; xxspltw 0,0,0 // convert b+c into V4SFmode -;; xvaddsp 12,12,0 // calculate b+c+d as V4SFmode -;; xvcvspbf16 12,12 // convert b+c+d into BFmode memory format -;; stxsihx 12,3,2 // store b+c+d -;; -;; With this peephole2, we can eliminate the xscvspdp and xscvdpspn -;; instructions. -;; -;; We keep the xxspltw between the two xvaddsp's in case the user -;; explicitly did a SFmode extract of element 0 and did a splat -;; operation. - -(define_peephole2 - [(set (match_operand:SF 0 "vsx_register_operand") - (unspec:SF - [(match_operand:V4SF 1 "vsx_register_operand")] - UNSPEC_VSX_CVSPDP)) - (set (match_operand:V4SF 2 "vsx_register_operand") - (unspec:V4SF [(match_dup 0)] UNSPEC_VSX_CVDPSPN))] - "REGNO (operands[1]) == REGNO (operands[2]) - || peep2_reg_dead_p (1, operands[1])" - [(set (match_dup 2) (match_dup 1))]) - -;; Vector Pack support. - -(define_expand "vec_pack_trunc_v4sf_v8hf" - [(match_operand:V8HF 0 "vfloat_operand") - (match_operand:V4SF 1 "vfloat_operand") - (match_operand:V4SF 2 "vfloat_operand")] - "TARGET_FLOAT16_HW" -{ - rtx r1 = gen_reg_rtx (V8HFmode); - rtx r2 = gen_reg_rtx (V8HFmode); - - emit_insn (gen_xvcvsphp_v8hf (r1, operands[1])); - emit_insn (gen_xvcvsphp_v8hf (r2, operands[2])); - rs6000_expand_extract_even (operands[0], r1, r2); - DONE; -}) - -(define_expand "vec_pack_trunc_v4sf_v8bf" - [(match_operand:V8BF 0 "vfloat_operand") - (match_operand:V4SF 1 "vfloat_operand") - (match_operand:V4SF 2 "vfloat_operand")] - "TARGET_BFLOAT16_HW" -{ - rtx r1 = gen_reg_rtx (V8BFmode); - rtx r2 = gen_reg_rtx (V8BFmode); - - emit_insn (gen_xvcvspbf16_v8bf (r1, operands[1])); - emit_insn (gen_xvcvspbf16_v8bf (r2, operands[2])); - rs6000_expand_extract_even (operands[0], r1, r2); - DONE; -}) - -;; Unfortunately the machine independent code assumes there is only one -;; 16-bit floating point type. This means we have to choose whether to -;; support packing _Float16 or __bfloat16. It looks like __bfloat16 is -;; more popular, so we choose __bfloat16 to be the default. - -(define_expand "vec_pack_trunc_v4sf" - [(match_operand:V8BF 0 "vfloat_operand") - (match_operand:V4SF 1 "vfloat_operand") - (match_operand:V4SF 2 "vfloat_operand")] - "TARGET_BFLOAT16_HW" -{ - rtx r1 = gen_reg_rtx (V8BFmode); - rtx r2 = gen_reg_rtx (V8BFmode); - - emit_insn (gen_xvcvspbf16_v8bf (r1, operands[1])); - emit_insn (gen_xvcvspbf16_v8bf (r2, operands[2])); - rs6000_expand_extract_even (operands[0], r1, r2); - DONE; -}) - -;; Used for vector conversion to _Float16 -(define_insn "xvcvsphp_v8hf" - [(set (match_operand:V8HF 0 "vsx_register_operand" "=wa") - (unspec:V8HF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_XVCVSPHP_V8HF))] - "TARGET_FLOAT16_HW" - "xvcvsphp %x0,%x1" -[(set_attr "type" "vecfloat")]) - -;; Used for vector conversion to __bfloat16 -(define_insn "xvcvspbf16_v8bf" - [(set (match_operand:V8BF 0 "vsx_register_operand" "=wa") - (unspec:V8BF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] - UNSPEC_XVCVSPBF16_V8BF))] - "TARGET_BFLOAT16_HW" - "xvcvspbf16 %x0,%x1" - [(set_attr "type" "vecfloat")]) - -;; Vector unpack support. Given the name is for the type being -;; unpacked, we can unpack both __bfloat16 and _Float16. - -;; Unpack vector _Float16 -(define_expand "vec_unpacks_hi_v8hf" - [(match_operand:V4SF 0 "vfloat_operand") - (match_operand:V8HF 1 "vfloat_operand")] - "TARGET_FLOAT16_HW" -{ - rtx reg = gen_reg_rtx (V8HFmode); - - rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); - emit_insn (gen_xvcvhpsp_v8hf (operands[0], reg)); - DONE; -}) - -(define_expand "vec_unpacks_lo_v8hf" - [(match_operand:V4SF 0 "vfloat_operand") - (match_operand:V8HF 1 "vfloat_operand")] - "TARGET_FLOAT16_HW" -{ - rtx reg = gen_reg_rtx (V8HFmode); - - rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); - emit_insn (gen_xvcvhpsp_v8hf (operands[0], reg)); - DONE; -}) - -;; Used for vector conversion from _Float16 -(define_insn "xvcvhpsp_v8hf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:V8HF 1 "vsx_register_operand" "wa")] - UNSPEC_CVT_FP16_TO_V4SF))] - "TARGET_BFLOAT16_HW" - "xvcvhpsp %x0,%x1" - [(set_attr "type" "vecperm")]) - -;; Unpack vector __bfloat16 -(define_expand "vec_unpacks_hi_v8bf" - [(match_operand:V4SF 0 "vfloat_operand") - (match_operand:V8BF 1 "vfloat_operand")] - "TARGET_BFLOAT16_HW" -{ - rtx reg = gen_reg_rtx (V8BFmode); - - rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); - emit_insn (gen_xvcvbf16spn_v8bf (operands[0], reg)); - DONE; -}) - -(define_expand "vec_unpacks_lo_v8bf" - [(match_operand:V4SF 0 "vfloat_operand") - (match_operand:V8BF 1 "vfloat_operand")] - "TARGET_BFLOAT16_HW" -{ - rtx reg = gen_reg_rtx (V8BFmode); - - rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); - emit_insn (gen_xvcvbf16spn_v8bf (operands[0], reg)); - DONE; -}) - -;; Used for vector conversion from __bfloat16 -(define_insn "xvcvbf16spn_v8bf" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:V8BF 1 "vsx_register_operand" "wa")] - UNSPEC_CVT_FP16_TO_V4SF))] - "TARGET_BFLOAT16_HW" - "xvcvbf16spn %x0,%x1" - [(set_attr "type" "vecperm")]) diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 408caf4521f0..647e89afb6a7 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -601,11 +601,6 @@ if (TARGET_VSX && op == CONST0_RTX (mode)) return 1; - /* Power9 needs to load HFmode constants from memory, Power10 can use - XXSPLTIW. */ - if (mode == HFmode && !TARGET_POWER10) - return 0; - /* Constants that can be generated with ISA 3.1 instructions are easy. */ vec_const_128bit_type vsx_const; if (TARGET_POWER10 && vec_const_128bit_to_bytes (op, mode, &vsx_const)) @@ -2171,100 +2166,3 @@ (and (match_code "subreg") (match_test "subreg_lowpart_offset (mode, GET_MODE (SUBREG_REG (op))) == SUBREG_BYTE (op)"))) - -;; Return 1 if this is a 16-bit floating point constant that can be -;; loaded with XXSPLTIW or is 0.0 that can be loaded with XXSPLTIB. -(define_predicate "fp16_xxspltiw_constant" - (match_code "const_double") -{ - if (!FP16_SCALAR_MODE_P (mode)) - return false; - - if (op == CONST0_RTX (mode)) - return true; - - if (!TARGET_PREFIXED) - return false; - - vec_const_128bit_type vsx_const; - if (!vec_const_128bit_to_bytes (op, mode, &vsx_const)) - return false; - - return constant_generates_xxspltiw (&vsx_const); -}) - -;; Return 1 if this is a 16-bit floating point operand that can be used -;; in an add, subtract, or multiply operation that uses the vector -;; conversion function. -(define_predicate "fp16_reg_or_constant_operand" - (match_code "reg,subreg,const_double") -{ - if (REG_P (op) || SUBREG_P (op)) - return vsx_register_operand (op, mode); - - if (CONST_DOUBLE_P (op)) - return fp16_xxspltiw_constant (op, mode); - - return false; -}) - -;; Match binary operators where we convert a BFmode operand into a -;; SFmode operand so that we can optimize the BFmode operation to do -;; the operation in vector mode rather than convverting the BFmode to a -;; V8BFmode vector, converting that V8BFmode vector to V4SFmode, and -;; then converting the V4SFmode element to SFmode scalar. -(define_predicate "fp16_binary_operator" - (match_code "plus,minus,mult,smax,smin")) - -;; Match bfloat16/float operands that can be optimized to do the -;; operation in V4SFmode. -(define_predicate "bfloat16_v4sf_operand" - (match_code "reg,subreg,const_double,float_extend,float_truncate") -{ - if (mode != BFmode && mode != SFmode) - return false; - - if (REG_P (op) || SUBREG_P (op)) - return register_operand (op, mode); - - if (CONST_DOUBLE_P (op)) - return true; - - if (GET_CODE (op) == FLOAT_EXTEND) - { - rtx op_arg = XEXP (op, 0); - return (mode == SFmode - && GET_MODE (op_arg) == BFmode - && (REG_P (op_arg) || SUBREG_P (op_arg))); - } - - if (GET_CODE (op) == FLOAT_TRUNCATE) - { - rtx op_arg = XEXP (op, 0); - return (mode == BFmode - && GET_MODE (op_arg) == SFmode - && (REG_P (op_arg) || SUBREG_P (op_arg))); - } - - return false; -}) - -;; Match an operand that originally was an BFmode value to prevent -;; operations involing only SFmode values from being converted to -;; BFmode. -(define_predicate "bfloat16_bf_operand" - (match_code "reg,subreg,const_double,float_extend") -{ - if (mode == BFmode || GET_MODE (op) == BFmode) - return true; - - if (mode != SFmode) - return false; - - if (GET_MODE (op) == SFmode - && GET_CODE (op) == FLOAT_EXTEND - && GET_MODE (XEXP (op, 0)) == BFmode) - return true; - - return false; -}) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 958b1392eee7..dfbb7d02157b 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -491,10 +491,6 @@ const char *rs6000_type_string (tree type_node) return "voidc*"; else if (type_node == float128_type_node) return "_Float128"; - else if (type_node == float16_type_node) - return "_Float16"; - else if (TARGET_BFLOAT16 && type_node == bfloat16_type_node) - return "__bfloat16"; else if (type_node == vector_pair_type_node) return "__vector_pair"; else if (type_node == vector_quad_type_node) @@ -760,22 +756,6 @@ rs6000_init_builtins (void) else ieee128_float_type_node = NULL_TREE; - /* __bfloat16 support. */ - if (TARGET_BFLOAT16) - { - if (!bfloat16_type_node) - { - bfloat16_type_node = make_node (REAL_TYPE); - TYPE_PRECISION (bfloat16_type_node) = 16; - SET_TYPE_MODE (bfloat16_type_node, BFmode); - layout_type (bfloat16_type_node); - t = build_qualified_type (bfloat16_type_node, TYPE_QUAL_CONST); - } - - lang_hooks.types.register_builtin_type (bfloat16_type_node, - "__bfloat16"); - } - /* Vector pair and vector quad support. */ vector_pair_type_node = make_node (OPAQUE_TYPE); SET_TYPE_MODE (vector_pair_type_node, OOmode); diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 3b4d4c4a09ab..70e6d4b1e6db 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -586,21 +586,6 @@ rs6000_target_modify_macros (bool define_p, if ((flags & OPTION_MASK_FLOAT128_HW) != 0) rs6000_define_or_undefine_macro (define_p, "__FLOAT128_HARDWARE__"); - /* 16-bit floating point support. */ - if ((flags & OPTION_MASK_FLOAT16) != 0) - { - rs6000_define_or_undefine_macro (define_p, "__FLOAT16__"); - if ((cpu_option & CPU_OPTION_POWER9_MASK) != 0) - rs6000_define_or_undefine_macro (define_p, "__FLOAT16_HW__"); - } - - if ((flags & OPTION_MASK_BFLOAT16) != 0) - { - rs6000_define_or_undefine_macro (define_p, "__BFLOAT16__"); - if ((cpu_option & CPU_OPTION_POWER10_MASK) != 0) - rs6000_define_or_undefine_macro (define_p, "__BFLOAT16_HW__"); - } - /* Tell the user if we are targeting CELL. */ if (rs6000_cpu == PROCESSOR_CELL) rs6000_define_or_undefine_macro (define_p, "__PPU__"); diff --git a/gcc/config/rs6000/rs6000-call.cc b/gcc/config/rs6000/rs6000-call.cc index 4d55ea2d1b36..8fe5652442e3 100644 --- a/gcc/config/rs6000/rs6000-call.cc +++ b/gcc/config/rs6000/rs6000-call.cc @@ -684,28 +684,6 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, " altivec instructions are disabled, use %qs" " to enable them", "-maltivec"); } - -#if !POWERPC_FLOAT16_DISABLE_WARNING - /* Warn that __bfloat16 and _Float16 might be returned differently in the - future. The issue is currently 16-bit floating point is returned in - floating point register #1 in 16-bit format. We may or may not want to - return it as a scalar 64-bit value. */ - if (fntype && warn_psabi && !cum->libcall) - { - static bool warned_about_float16_return = false; - - if (!warned_about_float16_return) - { - machine_mode ret_mode = TYPE_MODE (TREE_TYPE (fntype)); - - warned_about_float16_return = true; - if (ret_mode == BFmode || ret_mode == HFmode) - warning (OPT_Wpsabi, - "%s might be returned differently in the future", - ret_mode == BFmode ? "__bfloat16" : "_Float16"); - } - } -#endif } @@ -1663,24 +1641,6 @@ rs6000_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) return NULL_RTX; } -#if !POWERPC_FLOAT16_DISABLE_WARNING - /* Warn that _Float16 and __bfloat16 might be passed differently in the - future. The issue is currently 16-bit floating point values are passed in - floating point registers in the native 16-bit format. We may or may not - want to pass the value it as a scalar 64-bit value. */ - if (warn_psabi && !cum->libcall && FP16_SCALAR_MODE_P (mode)) - { - static bool warned_about_float16_call = false; - - if (!warned_about_float16_call) - { - warned_about_float16_call = true; - warning (OPT_Wpsabi, "%s might be passed differently in the future", - mode == BFmode ? "__bfloat16" : "_Float16"); - } - } -#endif - /* Return a marker to indicate whether CR1 needs to set or clear the bit that V.4 uses to say fp args were passed in registers. Assume that we don't need the marker for software floating point, diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 36b1d45b447e..233f01e9c615 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -85,16 +85,6 @@ | OPTION_MASK_ALTIVEC \ | OPTION_MASK_VSX) -/* Determine whether to enable 16-bit floating point types on power8 systems - and above. */ -#if POWERPC_FLOAT16_DEFAULT -#define TARGET_16BIT_FLOATING_POINT (OPTION_MASK_BFLOAT16 \ - | OPTION_MASK_FLOAT16) - -#else -#define TARGET_16BIT_FLOATING_POINT 0 -#endif - /* For now, don't provide an embedded version of ISA 2.07. Do not set power8 fusion here, instead set it in rs6000.cc if we are tuning for a power8 system. */ @@ -103,8 +93,7 @@ | OPTION_MASK_CRYPTO \ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_QUAD_MEMORY \ - | OPTION_MASK_QUAD_MEMORY_ATOMIC \ - | TARGET_16BIT_FLOATING_POINT) + | OPTION_MASK_QUAD_MEMORY_ATOMIC) /* ISA masks setting fusion options. */ #define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \ @@ -164,7 +153,6 @@ /* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */ #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ - | OPTION_MASK_BFLOAT16 \ | OPTION_MASK_CMPB \ | OPTION_MASK_CRYPTO \ | OPTION_MASK_DFP \ @@ -172,7 +160,6 @@ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_FLOAT128_KEYWORD \ - | OPTION_MASK_FLOAT16 \ | OPTION_MASK_FPRND \ | OPTION_MASK_P10_FUSION \ | OPTION_MASK_HTM \ diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 001dc1fc7f4b..4619142d197b 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -250,7 +250,6 @@ typedef struct { bool all_words_same; /* Are the words all equal? */ bool all_half_words_same; /* Are the half words all equal? */ bool all_bytes_same; /* Are the bytes all equal? */ - machine_mode mode; /* Original constant mode. */ } vec_const_128bit_type; extern bool vec_const_128bit_to_bytes (rtx, machine_mode, @@ -258,21 +257,6 @@ extern bool vec_const_128bit_to_bytes (rtx, machine_mode, extern unsigned constant_generates_lxvkq (vec_const_128bit_type *); extern unsigned constant_generates_xxspltiw (vec_const_128bit_type *); extern unsigned constant_generates_xxspltidp (vec_const_128bit_type *); - -/* From float16.cc. */ -/* Optimize bfloat16 and float16 operations. */ -enum fp16_operation { - FP16_BINARY, /* Bfloat16/float16 binary op. */ - FP16_FMA, /* (a * b) + c. */ - FP16_FMS, /* (a * b) - c. */ - FP16_NFMA, /* - ((a * b) + c). */ - FP16_NFMS /* - ((a * b) - c). */ -}; - -extern void fp16_vectorization (enum rtx_code, rtx, rtx, rtx, rtx, - enum fp16_operation); -extern void bfloat16_operation_as_v4sf (enum rtx_code, rtx, rtx, rtx, rtx, - enum fp16_operation); #endif /* RTX_CODE */ #ifdef TREE_CODE diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 40c479bef858..6d57d3fd1784 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1896,8 +1896,7 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode) if (ALTIVEC_REGNO_P (regno)) { - if (GET_MODE_SIZE (mode) < 16 && !reg_addr[mode].scalar_in_vmx_p - && !FP16_SCALAR_MODE_P (mode)) + if (GET_MODE_SIZE (mode) < 16 && !reg_addr[mode].scalar_in_vmx_p) return 0; return ALTIVEC_REGNO_P (last_regno); @@ -1987,8 +1986,7 @@ static bool rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2) { if (mode1 == PTImode || mode1 == OOmode || mode1 == XOmode - || mode2 == PTImode || mode2 == OOmode || mode2 == XOmode - || FP16_SCALAR_MODE_P (mode1) || FP16_SCALAR_MODE_P (mode2)) + || mode2 == PTImode || mode2 == OOmode || mode2 == XOmode) return mode1 == mode2; if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1)) @@ -2254,8 +2252,6 @@ rs6000_debug_reg_global (void) DImode, TImode, PTImode, - BFmode, - HFmode, SFmode, DFmode, TFmode, @@ -2636,14 +2632,8 @@ rs6000_setup_reg_addr_masks (void) /* SDmode is special in that we want to access it only via REG+REG addressing on power7 and above, since we want to use the LFIWZX and - STFIWZX instructions to load it. - - Never allow offset addressing for 16-bit floating point modes, since - it is expected that 16-bit floating point should always go into the - vector registers and we only have indexed and indirect 16-bit loads to - VSR registers. */ - bool indexed_only_p = ((m == SDmode && TARGET_NO_SDMODE_STACK) - || FP16_SCALAR_MODE_P (m)); + STFIWZX instructions to load it. */ + bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK); any_addr_mask = 0; for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++) @@ -2692,7 +2682,6 @@ rs6000_setup_reg_addr_masks (void) && !complex_p && (m != E_DFmode || !TARGET_VSX) && (m != E_SFmode || !TARGET_P8_VECTOR) - && !FP16_SCALAR_MODE_P (m) && !small_int_vsx_p) { addr_mask |= RELOAD_REG_PRE_INCDEC; @@ -2946,20 +2935,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_vector_align[V1TImode] = 128; } - /* _Float16 support. */ - if (TARGET_FLOAT16) - { - rs6000_vector_mem[HFmode] = VECTOR_VSX; - rs6000_vector_align[HFmode] = 16; - } - - /* _bfloat16 support. */ - if (TARGET_BFLOAT16) - { - rs6000_vector_mem[BFmode] = VECTOR_VSX; - rs6000_vector_align[BFmode] = 16; - } - /* DFmode, see if we want to use the VSX unit. Memory is handled differently, so don't set rs6000_vector_mem. */ if (TARGET_VSX) @@ -3074,18 +3049,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_di_load; } - if (TARGET_FLOAT16) - { - reg_addr[HFmode].reload_store = CODE_FOR_reload_hf_di_store; - reg_addr[HFmode].reload_load = CODE_FOR_reload_hf_di_load; - } - - if (TARGET_BFLOAT16) - { - reg_addr[BFmode].reload_store = CODE_FOR_reload_bf_di_store; - reg_addr[BFmode].reload_load = CODE_FOR_reload_bf_di_load; - } - /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are available. */ if (TARGET_NO_SDMODE_STACK) @@ -3186,18 +3149,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_si_load; } - if (TARGET_FLOAT16) - { - reg_addr[HFmode].reload_store = CODE_FOR_reload_hf_si_store; - reg_addr[HFmode].reload_load = CODE_FOR_reload_hf_si_load; - } - - if (TARGET_BFLOAT16) - { - reg_addr[BFmode].reload_store = CODE_FOR_reload_bf_si_store; - reg_addr[BFmode].reload_load = CODE_FOR_reload_bf_si_load; - } - /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are available. */ if (TARGET_NO_SDMODE_STACK) @@ -3937,23 +3888,6 @@ rs6000_option_override_internal (bool global_init_p) } } - /* -mfloat16 and -mbfloat16 needs power8 at a minimum in order to load up - 16-bit values into vector registers via loads/stores from GPRs and then - using direct moves. */ - if (TARGET_FLOAT16 && !TARGET_POWER8) - { - rs6000_isa_flags &= ~OPTION_MASK_FLOAT16; - if (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT16) - error ("%qs requires at least %qs", "-mfloat16", "-mcpu=power8"); - } - - if (TARGET_BFLOAT16 && !TARGET_POWER8) - { - rs6000_isa_flags &= ~OPTION_MASK_BFLOAT16; - if (rs6000_isa_flags_explicit & OPTION_MASK_BFLOAT16) - error ("%qs requires at least %qs", "-mbfloat16", "-mcpu=power8"); - } - /* If hard-float/altivec/vsx were explicitly turned off then don't allow the -mcpu setting to enable options that conflict. */ if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX) @@ -6517,12 +6451,9 @@ easy_altivec_constant (rtx op, machine_mode mode) else if (mode != GET_MODE (op)) return 0; - /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy constants. - Likewise, don't handle 16-bit floating point constants here, unless they - are 0.0. */ - if (mode == V2DFmode - || FP16_SCALAR_MODE_P (mode) - || FP16_VECTOR_MODE_P (mode)) + /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy + constants. */ + if (mode == V2DFmode) return zero_constant (op, mode) ? 8 : 0; else if (mode == V2DImode) @@ -7130,15 +7061,6 @@ rs6000_expand_vector_init (rtx target, rtx vals) return; } - /* Special case splats of 16-bit floating point. */ - if (all_same && FP16_VECTOR_MODE_P (mode)) - { - rtx op0 = force_reg (GET_MODE_INNER (mode), XVECEXP (vals, 0, 0)); - rtx dup = gen_rtx_VEC_DUPLICATE (mode, op0); - emit_insn (gen_rtx_SET (target, dup)); - return; - } - /* Special case initializing vector short/char that are splats if we are on 64-bit systems with direct move. */ if (all_same && TARGET_DIRECT_MOVE_64BIT @@ -8799,13 +8721,6 @@ reg_offset_addressing_ok_p (machine_mode mode) return mode_supports_dq_form (mode); break; - /* For 16-bit floating point types, do not allow offset addressing, since - it is assumed that most of the use will be in vector registers, and we - only have reg+reg addressing for 16-bit modes. */ - case E_BFmode: - case E_HFmode: - return false; - /* The vector pair/quad types support offset addressing if the underlying vectors support offset addressing. */ case E_OOmode: @@ -9096,13 +9011,6 @@ rs6000_legitimate_offset_address_p (machine_mode mode, rtx x, extra = 0; switch (mode) { - /* For 16-bit floating point types, do not allow offset addressing, since - it is assumed that most of the use will be in vector registers, and we - only have reg+reg addressing for 16-bit modes. */ - case E_BFmode: - case E_HFmode: - return false; - case E_DFmode: case E_DDmode: case E_DImode: @@ -9204,11 +9112,6 @@ macho_lo_sum_memory_operand (rtx x, machine_mode mode) static bool legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict) { - /* For 16-bit floating point types, do not allow offset addressing, since - it is assumed that most of the use will be in vector registers, and we - only have reg+reg addressing for 16-bit modes. */ - if (FP16_SCALAR_MODE_P (mode)) - return false; if (GET_CODE (x) != LO_SUM) return false; if (!REG_P (XEXP (x, 0))) @@ -12805,9 +12708,6 @@ rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type, && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE) || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE))) { - if (FP16_SCALAR_MODE_P (mode)) - return true; - if (TARGET_POWERPC64) { /* ISA 2.07: MTVSRD or MVFVSRD. */ @@ -13595,11 +13495,6 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass) || mode_supports_dq_form (mode)) return rclass; - /* IEEE 16-bit and bfloat16 don't support offset addressing, but they can - go in any floating point/vector register. */ - if (FP16_SCALAR_MODE_P (mode)) - return rclass; - /* If this is a scalar floating point value and we don't have D-form addressing, prefer the traditional floating point registers so that we can use D-form (register+offset) addressing. */ @@ -13829,9 +13724,6 @@ rs6000_can_change_mode_class (machine_mode from, unsigned from_size = GET_MODE_SIZE (from); unsigned to_size = GET_MODE_SIZE (to); - if (FP16_SCALAR_MODE_P (from) || FP16_SCALAR_MODE_P (to)) - return from_size == to_size; - if (from_size != to_size) { enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS; @@ -23118,7 +23010,7 @@ rs6000_load_constant_and_splat (machine_mode mode, REAL_VALUE_TYPE dconst) { rtx reg; - if (mode == SFmode || mode == DFmode || FP16_SCALAR_MODE_P (mode)) + if (mode == SFmode || mode == DFmode) { rtx d = const_double_from_real_value (dconst, mode); reg = force_reg (mode, d); @@ -24445,8 +24337,6 @@ rs6000_scalar_mode_supported_p (scalar_mode mode) return default_decimal_float_supported_p (); else if (TARGET_FLOAT128_TYPE && (mode == KFmode || mode == IFmode)) return true; - else if (FP16_SCALAR_MODE_P (mode)) - return true; else return default_scalar_mode_supported_p (mode); } @@ -24498,9 +24388,6 @@ rs6000_floatn_mode (int n, bool extended) { switch (n) { - case 16: - return TARGET_FLOAT16 ? SFmode : opt_scalar_float_mode (); - case 32: return DFmode; @@ -24522,9 +24409,6 @@ rs6000_floatn_mode (int n, bool extended) { switch (n) { - case 16: - return TARGET_FLOAT16 ? HFmode : opt_scalar_float_mode (); - case 32: return SFmode; @@ -24629,7 +24513,6 @@ struct rs6000_opt_mask { static struct rs6000_opt_mask const rs6000_opt_masks[] = { { "altivec", OPTION_MASK_ALTIVEC, false, true }, - { "bfloat16", OPTION_MASK_BFLOAT16, false, true }, { "block-ops-unaligned-vsx", OPTION_MASK_BLOCK_OPS_UNALIGNED_VSX, false, true }, { "block-ops-vector-pair", OPTION_MASK_BLOCK_OPS_VECTOR_PAIR, @@ -24645,7 +24528,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "fprnd", OPTION_MASK_FPRND, false, true }, { "hard-dfp", OPTION_MASK_DFP, false, true }, { "htm", OPTION_MASK_HTM, false, true }, - { "float16", OPTION_MASK_FLOAT16, false, true }, { "isel", OPTION_MASK_ISEL, false, true }, { "mfcrf", OPTION_MASK_MFCRF, false, true }, { "mfpgpr", 0, false, true }, @@ -29124,37 +29006,24 @@ constant_fp_to_128bit_vector (rtx op, const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op); long real_words[VECTOR_128BIT_WORDS]; - /* For 16-bit floating point, the constant doesn't fill the whole 32-bit - word. Deal with it here, storing the bytes in big endian fashion. */ - if (FP16_SCALAR_MODE_P (mode)) - { - real_to_target (real_words, rtype, mode); - info->bytes[byte_num] = (unsigned char) (real_words[0] >> 8); - info->bytes[byte_num+1] = (unsigned char) (real_words[0]); - } - - else - { - /* Make sure we don't overflow the real_words array and that it is filled - completely. */ - gcc_assert (num_words <= VECTOR_128BIT_WORDS && (bitsize % 32) == 0); + /* Make sure we don't overflow the real_words array and that it is + filled completely. */ + gcc_assert (num_words <= VECTOR_128BIT_WORDS && (bitsize % 32) == 0); - real_to_target (real_words, rtype, mode); + real_to_target (real_words, rtype, mode); - /* Iterate over each 32-bit word in the floating point constant. The - real_to_target function puts out words in target endian fashion. We - need to arrange the order so that the bytes are written in big endian - order. */ - for (unsigned num = 0; num < num_words; num++) - { - unsigned endian_num = (BYTES_BIG_ENDIAN - ? num - : num_words - 1 - num); + /* Iterate over each 32-bit word in the floating point constant. The + real_to_target function puts out words in target endian fashion. We need + to arrange the order so that the bytes are written in big endian order. */ + for (unsigned num = 0; num < num_words; num++) + { + unsigned endian_num = (BYTES_BIG_ENDIAN + ? num + : num_words - 1 - num); - unsigned uvalue = real_words[endian_num]; - for (int shift = 32 - 8; shift >= 0; shift -= 8) - info->bytes[byte_num++] = (uvalue >> shift) & 0xff; - } + unsigned uvalue = real_words[endian_num]; + for (int shift = 32 - 8; shift >= 0; shift -= 8) + info->bytes[byte_num++] = (uvalue >> shift) & 0xff; } /* Mark that this constant involves floating point. */ @@ -29193,7 +29062,6 @@ vec_const_128bit_to_bytes (rtx op, return false; /* Set up the bits. */ - info->mode = mode; switch (GET_CODE (op)) { /* Integer constants, default to double word. */ @@ -29421,10 +29289,6 @@ constant_generates_xxspltiw (vec_const_128bit_type *vsx_const) if (!TARGET_SPLAT_WORD_CONSTANT || !TARGET_PREFIXED || !TARGET_VSX) return 0; - /* HFmode/BFmode constants can always use XXSPLTIW. */ - if (FP16_SCALAR_MODE_P (vsx_const->mode)) - return 1; - if (!vsx_const->all_words_same) return 0; diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 7850affe6afc..c31fd1a7e0f5 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -343,26 +343,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); || ((MODE) == TDmode) \ || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))) -/* Do we have conversion support in hardware for the 16-bit floating point? */ -#define TARGET_BFLOAT16_HW (TARGET_BFLOAT16 && TARGET_POWER10) -#define TARGET_FLOAT16_HW (TARGET_FLOAT16 && TARGET_POWER9) - -/* Is this a valid 16-bit scalar floating point mode? */ -#define FP16_SCALAR_MODE_P(MODE) \ - (((MODE) == HFmode && TARGET_FLOAT16) \ - || ((MODE) == BFmode && TARGET_BFLOAT16)) - -/* Is this a valid 16-bit scalar floating point mode that has hardware - conversions? */ -#define FP16_HW_SCALAR_MODE_P(MODE) \ - (((MODE) == HFmode && TARGET_FLOAT16_HW) \ - || ((MODE) == BFmode && TARGET_BFLOAT16_HW)) - -/* Is this a valid 16-bit vector floating point mode? */ -#define FP16_VECTOR_MODE_P(MODE) \ - (((MODE) == V8HFmode && TARGET_FLOAT16) \ - || ((MODE) == V8BFmode && TARGET_BFLOAT16)) - /* Return true for floating point that does not use a vector register. */ #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \ (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE)) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index bc5baf1bdbe7..f6cb7d7f4819 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -714,8 +714,6 @@ ; A generic w/d attribute, for things like cmpw/cmpd. (define_mode_attr wd [(QI "b") (HI "h") - (BF "h") - (HF "h") (SI "w") (DI "d") (V16QI "b") @@ -15893,4 +15891,3 @@ (include "htm.md") (include "fusion.md") (include "pcrel-opt.md") -(include "float16.md") diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 7acc539f42a7..31852e02aa0f 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -638,14 +638,6 @@ mieee128-constant Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save Generate (do not generate) code that uses the LXVKQ instruction. -mfloat16 -Target Mask(FLOAT16) Var(rs6000_isa_flags) -Enable or disable _Float16 support. - -mbfloat16 -Target Mask(BFLOAT16) Var(rs6000_isa_flags) -Enable or disable __bfloat16 support. - ; Documented parameters -param=rs6000-vect-unroll-limit= diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000 index c8f19865311c..a5d1c27424f3 100644 --- a/gcc/config/rs6000/t-rs6000 +++ b/gcc/config/rs6000/t-rs6000 @@ -87,10 +87,6 @@ rs6000-c.o: $(srcdir)/config/rs6000/rs6000-c.cc rs6000-builtins.h $(COMPILE) $< $(POSTCOMPILE) -float16.o: $(srcdir)/config/rs6000/float16.cc - $(COMPILE) $< - $(POSTCOMPILE) - #$(srcdir)/config/rs6000/fusion.md: $(srcdir)/config/rs6000/genfusion.pl # $(srcdir)/config/rs6000/genfusion.pl > $(srcdir)/config/rs6000/fusion.md diff --git a/libgcc/config.host b/libgcc/config.host index ea5853d34b79..82ea1772f516 100644 --- a/libgcc/config.host +++ b/libgcc/config.host @@ -1302,18 +1302,6 @@ powerpc*-*-linux*) tmake_file="${tmake_file} rs6000/t-float128-p10-hw" fi - if test $libgcc_cv_powerpc_float16 = yes; then - tmake_file="${tmake_file} rs6000/t-float16" - fi - - if test $libgcc_cv_powerpc_bfloat16 = yes; then - tmake_file="${tmake_file} rs6000/t-bfloat16" - - if test $libgcc_cv_powerpc_bfloat16 = yes; then - tmake_file="${tmake_file} rs6000/t-both-fp16" - fi - fi - extra_parts="$extra_parts ecrti.o ecrtn.o ncrti.o ncrtn.o" md_unwind_header=rs6000/linux-unwind.h ;; diff --git a/libgcc/config/rs6000/sfp-machine.h b/libgcc/config/rs6000/sfp-machine.h index 642d2fc4f215..f0ede0e042a3 100644 --- a/libgcc/config/rs6000/sfp-machine.h +++ b/libgcc/config/rs6000/sfp-machine.h @@ -22,9 +22,6 @@ typedef unsigned int UTItype __attribute__ ((mode (TI))); #define _FP_I_TYPE int #endif /* 32-bits */ -#define _FP_NANFRAC_H _FP_QNANBIT_H -#define _FP_NANFRAC_B _FP_QNANBIT_B - /* The type of the result of a floating point comparison. This must match `__libgcc_cmp_return__' in GCC for the target. */ typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__))); @@ -65,8 +62,6 @@ typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__))); #define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1 #endif -#define _FP_NANSIGN_H 1 -#define _FP_NANSIGN_B 1 #define _FP_NANSIGN_S 0 #define _FP_NANSIGN_D 0 #define _FP_NANSIGN_Q 0 @@ -166,48 +161,3 @@ void __sfp_handle_exceptions (int); # define strong_alias(name, aliasname) _strong_alias(name, aliasname) # define _strong_alias(name, aliasname) \ extern __typeof (name) aliasname __attribute__ ((alias (#name))); - -/* Add prototypes for the HFmode and BFmode functions. */ -typedef double DFtype2; -typedef float SFtype2; -typedef int DItype2 __attribute__ ((mode (DI))); -typedef unsigned int UDItype2 __attribute__ ((mode (DI))); -typedef int SItype2 __attribute__ ((mode (SI))); -typedef unsigned int USItype2 __attribute__ ((mode (SI))); - -#ifdef __FLOAT16__ -typedef float HFtype2 __attribute__ ((mode (HF))); - -extern CMPtype __eqhf2 (HFtype2, HFtype2); -extern DFtype2 __extendhfdf2 (HFtype2); -extern SFtype2 __extendhfsf2 (HFtype2); -extern DItype2 __fixhfdi (HFtype2); -extern SItype2 __fixhfsi (HFtype2); -extern UDItype2 __fixunshfdi (HFtype2); -extern USItype2 __fixunshfsi (HFtype2); -extern HFtype2 __floatdihf (DItype2); -extern HFtype2 __floatsihf (SItype2); -extern HFtype2 __floatundihf (UDItype2); -extern HFtype2 __floatunsihf (USItype2); -extern HFtype2 __truncdfhf2 (DFtype2); -extern HFtype2 __truncsfhf2 (SFtype2); -#endif - -#ifdef __BFLOAT16__ -typedef float BFtype2 __attribute__ ((mode (BF))); - -extern SFtype2 __extendbfsf2 (BFtype2); -extern BFtype2 __floatdibf (DItype2); -extern BFtype2 __floatsibf (SItype2); -extern BFtype2 __floatundibf (UDItype2); -extern BFtype2 __floatunsibf (USItype2); -extern BFtype2 __truncdfbf2 (DFtype2); -extern BFtype2 __truncsfbf2 (SFtype2); -#endif - -#if defined(__FLOAT16__) && defined(__BFLOAT16__) -extern HFtype2 __truncbfhf2 (BFtype2); -extern BFtype2 __trunchfbf2 (HFtype2); -#endif - - diff --git a/libgcc/config/rs6000/t-bfloat16 b/libgcc/config/rs6000/t-bfloat16 deleted file mode 100644 index cade2439c780..000000000000 --- a/libgcc/config/rs6000/t-bfloat16 +++ /dev/null @@ -1,30 +0,0 @@ -# __bfloat16 library support - -bfp16_funcs = extendbfsf2 floatdibf floatsibf floatundibf floatunsibf \ - truncdfbf2 truncsfbf2 - -bfp16_src = $(addprefix $(srcdir)/soft-fp/,$(addsuffix .c,$(bfp16_funcs))) -bfp16_obj = $(addsuffix $(objext),$(bfp16_funcs)) - -BFP16_CFLAGS = -mbfloat16 -Wno-psabi \ - -I$(srcdir)/soft-fp \ - -I$(srcdir)/config/rs6000 \ - -$(bfp16_obj) : INTERNAL_CFLAGS += $(BFP16_CFLAGS) - -# For now, only put it in the static library -# LIB2ADD += $(bfp16_src) - -LIB2ADD_ST += $(bfp16_src) - -.PHONY: test-bfloat16 clean-bfloat16 - -test-bfloat16: - @echo "bfp16_src:"; \ - for x in $(bfp16_src); do echo " $$x"; done; \ - echo; \ - echo "bfp16_obj:"; \ - for x in $(bfp16_obj); do echo " $$x"; done; - -clean-bfloat16: - @$(MULTICLEAN) multi-clean DO=clean-float16 diff --git a/libgcc/config/rs6000/t-both-fp16 b/libgcc/config/rs6000/t-both-fp16 deleted file mode 100644 index d51b7abbf086..000000000000 --- a/libgcc/config/rs6000/t-both-fp16 +++ /dev/null @@ -1,28 +0,0 @@ -# Conversion between __bfloat16 and _Float16 - -both_fp16_funcs = truncbfhf2 trunchfbf2 -both_fp16_src = $(addprefix $(srcdir)/soft-fp/,$(addsuffix .c,$(both_fp16_funcs))) -both_fp16_obj = $(addsuffix $(objext),$(both_fp16_funcs)) - -BOTH_FP16_CFLAGS = -mfloat16 -mbfloat16 -Wno-psabi \ - -I$(srcdir)/soft-fp \ - -I$(srcdir)/config/rs6000 \ - -$(both_fp16_obj) : INTERNAL_CFLAGS += $(BOTH_FP16_CFLAGS) - -# For now, only put it in the static library -# LIB2ADD += $(both_fp16_src) - -LIB2ADD_ST += $(both_fp16_src) - -.PHONY: test-both-fp16 clean-both-fp16 - -test-both-fp16: - @echo "both_fp16_src:"; \ - for x in $(both_fp16_src); do echo " $$x"; done; \ - echo; \ - echo "both_fp16_obj:"; \ - for x in $(both_fp16_obj); do echo " $$x"; done; - -clean-both-fp16: - @$(MULTICLEAN) multi-clean DO=clean-both-fp16 diff --git a/libgcc/config/rs6000/t-float16 b/libgcc/config/rs6000/t-float16 deleted file mode 100644 index f961097e85d1..000000000000 --- a/libgcc/config/rs6000/t-float16 +++ /dev/null @@ -1,31 +0,0 @@ -# _Float16 library support - -fp16_funcs = eqhf2 extendhfdf2 extendhfsf2 \ - fixhfdi fixhfsi fixunshfdi fixunshfsi \ - floatdihf floatsihf floatundihf floatunsihf \ - truncdfhf2 truncsfhf2 - -fp16_src = $(addprefix $(srcdir)/soft-fp/,$(addsuffix .c,$(fp16_funcs))) -fp16_obj = $(addsuffix $(objext),$(fp16_funcs)) - -FP16_CFLAGS = -mfloat16 -Wno-psabi \ - -I$(srcdir)/soft-fp -I$(srcdir)/config/rs6000 - -$(fp16_obj) : INTERNAL_CFLAGS += $(FP16_CFLAGS) - -# For now, only put it in the static library -# LIB2ADD += $(fp16_src) - -LIB2ADD_ST += $(fp16_src) - -.PHONY: test-float16 clean-float16 - -test-float16: - @echo "fp16_src:"; \ - for x in $(fp16_src); do echo " $$x"; done; \ - echo; \ - echo "fp16_obj:"; \ - for x in $(fp16_obj); do echo " $$x"; done; - -clean-float16: - @$(MULTICLEAN) multi-clean DO=clean-float16 diff --git a/libgcc/configure b/libgcc/configure index ed7ea9e7d621..d5e80d227ff6 100755 --- a/libgcc/configure +++ b/libgcc/configure @@ -5188,8 +5188,6 @@ case ${host} in # check if we have VSX (ISA 2.06) support to build the software libraries, and # whether the assembler can handle xsaddqp for hardware support. Also check if # a new glibc is being used so that __builtin_cpu_supports can be used. -# -# Add float16 support also powerpc*-*-linux*) saved_CFLAGS="$CFLAGS" CFLAGS="$CFLAGS -mabi=altivec -mvsx -mfloat128" @@ -5284,48 +5282,6 @@ fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_powerpc_3_1_float128_hw" >&5 $as_echo "$libgcc_cv_powerpc_3_1_float128_hw" >&6; } CFLAGS="$saved_CFLAGS" - - CFLAGS="$CFLAGS -mfloat16 -Wno-psabi" - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the PowerPC can build the _Float16 libraries" >&5 -$as_echo_n "checking whether the PowerPC can build the _Float16 libraries... " >&6; } -if ${libgcc_cv_powerpc_float16+:} false; then : - $as_echo_n "(cached) " >&6 -else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -/* end confdefs.h. */ -_Float16 addf16 (_Float16 a, _Float16 b) { return a + b; } -_ACEOF -if ac_fn_c_try_compile "$LINENO"; then : - libgcc_cv_powerpc_float16=yes -else - libgcc_cv_powerpc_float16=no -fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext -fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_powerpc_float16" >&5 -$as_echo "$libgcc_cv_powerpc_float16" >&6; } - CFLAGS="$saved_CFLAGS" - - CFLAGS="$CFLAGS -mbfloat16 -Wno-psabi" - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the PowerPC can build __bfloat16 libraries" >&5 -$as_echo_n "checking whether the PowerPC can build __bfloat16 libraries... " >&6; } -if ${libgcc_cv_powerpc_bfloat16+:} false; then : - $as_echo_n "(cached) " >&6 -else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -/* end confdefs.h. */ -__bfloat16 addbf16 (__bfloat16 a, __bfloat16 b) { return a + b; } -_ACEOF -if ac_fn_c_try_compile "$LINENO"; then : - libgcc_cv_powerpc_bfloat16=yes -else - libgcc_cv_powerpc_bfloat16=no -fi -rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext -fi -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_powerpc_bfloat16" >&5 -$as_echo "$libgcc_cv_powerpc_bfloat16" >&6; } - CFLAGS="$saved_CFLAGS" esac # Collect host-machine-specific information. diff --git a/libgcc/configure.ac b/libgcc/configure.ac index 464acdee14c3..65cd3c6aa1a5 100644 --- a/libgcc/configure.ac +++ b/libgcc/configure.ac @@ -407,8 +407,6 @@ case ${host} in # check if we have VSX (ISA 2.06) support to build the software libraries, and # whether the assembler can handle xsaddqp for hardware support. Also check if # a new glibc is being used so that __builtin_cpu_supports can be used. -# -# Add float16 support also powerpc*-*-linux*) saved_CFLAGS="$CFLAGS" CFLAGS="$CFLAGS -mabi=altivec -mvsx -mfloat128" @@ -467,24 +465,6 @@ powerpc*-*-linux*) [libgcc_cv_powerpc_3_1_float128_hw=yes], [libgcc_cv_powerpc_3_1_float128_hw=no])]) CFLAGS="$saved_CFLAGS" - - CFLAGS="$CFLAGS -mfloat16 -Wno-psabi" - AC_CACHE_CHECK([whether the PowerPC can build the _Float16 libraries], - [libgcc_cv_powerpc_float16], - [AC_COMPILE_IFELSE( - [AC_LANG_SOURCE([_Float16 addf16 (_Float16 a, _Float16 b) { return a + b; }])], - [libgcc_cv_powerpc_float16=yes], - [libgcc_cv_powerpc_float16=no])]) - CFLAGS="$saved_CFLAGS" - - CFLAGS="$CFLAGS -mbfloat16 -Wno-psabi" - AC_CACHE_CHECK([whether the PowerPC can build __bfloat16 libraries], - [libgcc_cv_powerpc_bfloat16], - [AC_COMPILE_IFELSE( - [AC_LANG_SOURCE([__bfloat16 addbf16 (__bfloat16 a, __bfloat16 b) { return a + b; }])], - [libgcc_cv_powerpc_bfloat16=yes], - [libgcc_cv_powerpc_bfloat16=no])]) - CFLAGS="$saved_CFLAGS" esac # Collect host-machine-specific information. diff --git a/libstdc++-v3/include/std/limits b/libstdc++-v3/include/std/limits index 24fb375c9cb0..49ce7c935e9d 100644 --- a/libstdc++-v3/include/std/limits +++ b/libstdc++-v3/include/std/limits @@ -2067,16 +2067,9 @@ __glibcxx_float_n(128) quiet_NaN() _GLIBCXX_USE_NOEXCEPT { return __gnu_cxx::__bfloat16_t(__builtin_nanf("")); } -#ifdef _ARCH_PPC - static _GLIBCXX_CONSTEXPR __gnu_cxx::__bfloat16_t - signaling_NaN() _GLIBCXX_USE_NOEXCEPT - { return __gnu_cxx::__bfloat16_t(__builtin_nansf("")); } - -#else static _GLIBCXX_CONSTEXPR __gnu_cxx::__bfloat16_t signaling_NaN() _GLIBCXX_USE_NOEXCEPT { return __builtin_nansf16b(""); } -#endif static _GLIBCXX_CONSTEXPR __gnu_cxx::__bfloat16_t denorm_min() _GLIBCXX_USE_NOEXCEPT
