> +;; SWAP
> +(define_insn "swap"
> + [(set (match_operand:QI 0 "register_operand" "=r")
> + (unspec:QI [(match_operand:QI 1 "register_operand" "0")]
> + UNSPEC_SWAP))]
> + ""
> + "swap %0"
> + [(set_attr "length" "1")
> + (set_attr "cc" "none")])
This is already properly represented as
(define_insn "*rotlqi3_4"
[(set (match_operand:QI 0 "register_operand" "=r")
(rotate:QI (match_operand:QI 1 "register_operand" "0")
(const_int 4)))]
""
"swap %0"
[(set_attr "length" "1")
(set_attr "cc" "none")])
you ought not need another copy; just have the builtin emit the rotate.
> +(define_insn "fmuls"
> + [(set (match_operand:HI 0 "a_register_operand" "=r")
> + (unspec:HI [(match_operand:QI 1 "a_register_operand" "r")
> + (match_operand:QI 2 "a_register_operand" "r")]
> + UNSPEC_FMULS))]
...
> +;; Registers from r16 to 24.
> +(define_predicate "a_register_operand"
> + (and (match_code "reg")
> + (match_test "REGNO (op) >= 16 && REGNO (op) <= 24")))
These constraint/predicate pairs are wrong. You should use register_operand
for all of the operands, and proper constraints. I believe that the output
can simply use "=r", since HImode registers are already constrained to be
aligned; the inputs should be "a".
> + "AVR_HAVE_MUL"
> + "fmuls %1,%2
> + movw %0,r0
> + clr r1"
The rest of the port is fairly consistent using __zero_reg__ instead
of r1. You probably want to continue that.
r~
