While purging Windows code, I failed to remember that VMS has a 32-bit
mode as well, and thus this line still matters.
r~
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 38d40b5..abd96c7 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -177,6 +177,19 @@
(define_attr "cannot_copy" "false,true"
(const_string "false"))
+
+;; Used to control the "enabled" attribute on a per-instruction basis.
+(define_attr "isa" "base,bwx,max,fix,cix,vms"
+ (const_string "base"))
+
+(define_attr "enabled" ""
+ (cond [(eq_attr "isa" "bwx") (symbol_ref "TARGET_BWX")
+ (eq_attr "isa" "max") (symbol_ref "TARGET_MAX")
+ (eq_attr "isa" "fix") (symbol_ref "TARGET_FIX")
+ (eq_attr "isa" "cix") (symbol_ref "TARGET_CIX")
+ (eq_attr "isa" "vms") (symbol_ref "TARGET_ABI_OPEN_VMS")
+ ]
+ (const_int 1)))
;; Include scheduling descriptions.
@@ -1092,130 +1105,60 @@
operands[4] = GEN_INT (mask2);
})
-(define_expand "zero_extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "")
- (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
- ""
-{
- if (! TARGET_BWX)
- operands[1] = force_reg (QImode, operands[1]);
-})
-
-(define_insn "*zero_extendqihi2_bwx"
+(define_insn "zero_extendqihi2"
[(set (match_operand:HI 0 "register_operand" "=r,r")
- (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_BWX"
+ (zero_extend:HI
+ (match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))]
+ ""
"@
and %1,0xff,%0
ldbu %0,%1"
- [(set_attr "type" "ilog,ild")])
-
-(define_insn "*zero_extendqihi2_nobwx"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
- "! TARGET_BWX"
- "and %1,0xff,%0"
- [(set_attr "type" "ilog")])
-
-(define_expand "zero_extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
- ""
-{
- if (! TARGET_BWX)
- operands[1] = force_reg (QImode, operands[1]);
-})
+ [(set_attr "type" "ilog,ild")
+ (set_attr "isa" "*,bwx")])
-(define_insn "*zero_extendqisi2_bwx"
+(define_insn "zero_extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
- (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_BWX"
+ (zero_extend:SI
+ (match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))]
+ ""
"@
and %1,0xff,%0
ldbu %0,%1"
- [(set_attr "type" "ilog,ild")])
-
-(define_insn "*zero_extendqisi2_nobwx"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
- "! TARGET_BWX"
- "and %1,0xff,%0"
- [(set_attr "type" "ilog")])
-
-(define_expand "zero_extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
- ""
-{
- if (! TARGET_BWX)
- operands[1] = force_reg (QImode, operands[1]);
-})
+ [(set_attr "type" "ilog,ild")
+ (set_attr "isa" "*,bwx")])
-(define_insn "*zero_extendqidi2_bwx"
+(define_insn "zero_extendqidi2"
[(set (match_operand:DI 0 "register_operand" "=r,r")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_BWX"
+ (zero_extend:DI
+ (match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))]
+ ""
"@
and %1,0xff,%0
ldbu %0,%1"
- [(set_attr "type" "ilog,ild")])
-
-(define_insn "*zero_extendqidi2_nobwx"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
- "! TARGET_BWX"
- "and %1,0xff,%0"
- [(set_attr "type" "ilog")])
+ [(set_attr "type" "ilog,ild")
+ (set_attr "isa" "*,bwx")])
-(define_expand "zero_extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
- ""
-{
- if (! TARGET_BWX)
- operands[1] = force_reg (HImode, operands[1]);
-})
-
-(define_insn "*zero_extendhisi2_bwx"
+(define_insn "zero_extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
- (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_BWX"
+ (zero_extend:SI
+ (match_operand:HI 1 "reg_or_bwx_memory_operand" "r,m")))]
+ ""
"@
zapnot %1,3,%0
ldwu %0,%1"
- [(set_attr "type" "shift,ild")])
-
-(define_insn "*zero_extendhisi2_nobwx"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
- "! TARGET_BWX"
- "zapnot %1,3,%0"
- [(set_attr "type" "shift")])
-
-(define_expand "zero_extendhidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
- ""
-{
- if (! TARGET_BWX)
- operands[1] = force_reg (HImode, operands[1]);
-})
+ [(set_attr "type" "shift,ild")
+ (set_attr "isa" "*,bwx")])
-(define_insn "*zero_extendhidi2_bwx"
+(define_insn "zero_extendhidi2"
[(set (match_operand:DI 0 "register_operand" "=r,r")
- (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_BWX"
+ (zero_extend:DI
+ (match_operand:HI 1 "reg_or_bwx_memory_operand" "r,m")))]
+ ""
"@
zapnot %1,3,%0
ldwu %0,%1"
- [(set_attr "type" "shift,ild")])
-
-(define_insn "*zero_extendhidi2_nobwx"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
- ""
- "zapnot %1,3,%0"
- [(set_attr "type" "shift")])
+ [(set_attr "type" "shift,ild")
+ (set_attr "isa" "*,bwx")])
(define_insn "zero_extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=r")
@@ -1471,194 +1414,103 @@
"sra %r1,%2,%0"
[(set_attr "type" "shift")])
-(define_expand "extendqihi2"
- [(set (match_dup 2)
- (ashift:DI (match_operand:QI 1 "some_operand" "")
- (const_int 56)))
- (set (match_operand:HI 0 "register_operand" "")
- (ashiftrt:DI (match_dup 2)
- (const_int 56)))]
- ""
-{
- if (TARGET_BWX)
- {
- emit_insn (gen_extendqihi2x (operands[0],
- force_reg (QImode, operands[1])));
- DONE;
- }
-
- /* If we have an unaligned MEM, extend to DImode (which we do
- specially) and then copy to the result. */
- if (unaligned_memory_operand (operands[1], HImode))
- {
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_extendqidi2 (temp, operands[1]));
- emit_move_insn (operands[0], gen_lowpart (HImode, temp));
- DONE;
- }
-
- operands[0] = gen_lowpart (DImode, operands[0]);
- operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
- operands[2] = gen_reg_rtx (DImode);
-})
-
-(define_insn "extendqidi2x"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
+(define_insn "extendqihi2"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
"TARGET_BWX"
"sextb %1,%0"
[(set_attr "type" "shift")])
-(define_insn "extendhidi2x"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
- "TARGET_BWX"
- "sextw %1,%0"
- [(set_attr "type" "shift")])
-
-(define_insn "extendqisi2x"
+(define_insn "extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
"TARGET_BWX"
"sextb %1,%0"
[(set_attr "type" "shift")])
-(define_insn "extendhisi2x"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
- "TARGET_BWX"
- "sextw %1,%0"
- [(set_attr "type" "shift")])
-
-(define_insn "extendqihi2x"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
- "TARGET_BWX"
- "sextb %1,%0"
- [(set_attr "type" "shift")])
-
-(define_expand "extendqisi2"
- [(set (match_dup 2)
- (ashift:DI (match_operand:QI 1 "some_operand" "")
- (const_int 56)))
- (set (match_operand:SI 0 "register_operand" "")
- (ashiftrt:DI (match_dup 2)
- (const_int 56)))]
- ""
-{
- if (TARGET_BWX)
- {
- emit_insn (gen_extendqisi2x (operands[0],
- force_reg (QImode, operands[1])));
- DONE;
- }
-
- /* If we have an unaligned MEM, extend to a DImode form of
- the result (which we do specially). */
- if (unaligned_memory_operand (operands[1], QImode))
- {
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_extendqidi2 (temp, operands[1]));
- emit_move_insn (operands[0], gen_lowpart (SImode, temp));
- DONE;
- }
-
- operands[0] = gen_lowpart (DImode, operands[0]);
- operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
- operands[2] = gen_reg_rtx (DImode);
-})
-
(define_expand "extendqidi2"
- [(set (match_dup 2)
- (ashift:DI (match_operand:QI 1 "some_operand" "")
- (const_int 56)))
- (set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_dup 2)
- (const_int 56)))]
+ [(set (match_operand:DI 0 "register_operand" "")
+ (sign_extend:DI (match_operand:QI 1 "some_operand" "")))]
""
{
if (TARGET_BWX)
+ operands[1] = force_reg (QImode, operands[1]);
+ else
{
- emit_insn (gen_extendqidi2x (operands[0],
- force_reg (QImode, operands[1])));
- DONE;
- }
+ rtx x, t1, t2, i56;
- if (unaligned_memory_operand (operands[1], QImode))
- {
- rtx seq = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0));
- alpha_set_memflags (seq, operands[1]);
- emit_insn (seq);
- DONE;
- }
+ if (unaligned_memory_operand (operands[1], QImode))
+ {
+ x = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0));
+ alpha_set_memflags (x, operands[1]);
+ emit_insn (x);
+ DONE;
+ }
- operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
- operands[2] = gen_reg_rtx (DImode);
-})
+ t1 = gen_reg_rtx (DImode);
+ t2 = gen_reg_rtx (DImode);
+ i56 = GEN_INT (56);
-(define_expand "extendhisi2"
- [(set (match_dup 2)
- (ashift:DI (match_operand:HI 1 "some_operand" "")
- (const_int 48)))
- (set (match_operand:SI 0 "register_operand" "")
- (ashiftrt:DI (match_dup 2)
- (const_int 48)))]
- ""
-{
- if (TARGET_BWX)
- {
- emit_insn (gen_extendhisi2x (operands[0],
- force_reg (HImode, operands[1])));
+ x = gen_lowpart (DImode, force_reg (QImode, operands[1]));
+ emit_move_insn (t1, x);
+ emit_insn (gen_ashldi3 (t2, t1, i56));
+ emit_insn (gen_ashrdi3 (operands[0], t2, i56));
DONE;
}
+})
- /* If we have an unaligned MEM, extend to a DImode form of
- the result (which we do specially). */
- if (unaligned_memory_operand (operands[1], HImode))
- {
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_extendhidi2 (temp, operands[1]));
- emit_move_insn (operands[0], gen_lowpart (SImode, temp));
- DONE;
- }
+(define_insn "*extendqidi2_bwx"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
+ "TARGET_BWX"
+ "sextb %1,%0"
+ [(set_attr "type" "shift")])
- operands[0] = gen_lowpart (DImode, operands[0]);
- operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
- operands[2] = gen_reg_rtx (DImode);
-})
+(define_insn "extendhisi2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
+ "TARGET_BWX"
+ "sextw %1,%0"
+ [(set_attr "type" "shift")])
(define_expand "extendhidi2"
- [(set (match_dup 2)
- (ashift:DI (match_operand:HI 1 "some_operand" "")
- (const_int 48)))
- (set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_dup 2)
- (const_int 48)))]
+ [(set (match_operand:DI 0 "register_operand" "")
+ (sign_extend:DI (match_operand:HI 1 "some_operand" "")))]
""
{
if (TARGET_BWX)
+ operands[1] = force_reg (HImode, operands[1]);
+ else
{
- emit_insn (gen_extendhidi2x (operands[0],
- force_reg (HImode, operands[1])));
- DONE;
- }
+ rtx x, t1, t2, i48;
- if (unaligned_memory_operand (operands[1], HImode))
- {
- rtx seq = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0));
+ if (unaligned_memory_operand (operands[1], HImode))
+ {
+ x = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0));
+ alpha_set_memflags (x, operands[1]);
+ emit_insn (x);
+ DONE;
+ }
- alpha_set_memflags (seq, operands[1]);
- emit_insn (seq);
+ t1 = gen_reg_rtx (DImode);
+ t2 = gen_reg_rtx (DImode);
+ i48 = GEN_INT (48);
+
+ x = gen_lowpart (DImode, force_reg (HImode, operands[1]));
+ emit_move_insn (t1, x);
+ emit_insn (gen_ashldi3 (t2, t1, i48));
+ emit_insn (gen_ashrdi3 (operands[0], t2, i48));
DONE;
}
-
- operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
- operands[2] = gen_reg_rtx (DImode);
})
+(define_insn "*extendhidi2_bwx"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
+ "TARGET_BWX"
+ "sextw %1,%0"
+ [(set_attr "type" "shift")])
+
;; Here's how we sign extend an unaligned byte and halfword. Doing this
;; as a pattern saves one instruction. The code is similar to that for
;; the unaligned loads (see below).
@@ -4756,25 +4608,10 @@
;; are done via define_expand. Start with the floating-point insns, since
;; they are simpler.
-(define_insn "*movsf_nofix"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
- (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
- "TARGET_FPREGS && ! TARGET_FIX
- && (register_operand (operands[0], SFmode)
- || reg_or_0_operand (operands[1], SFmode))"
- "@
- cpys %R1,%R1,%0
- ld%, %0,%1
- bis $31,%r1,%0
- ldl %0,%1
- st%, %R1,%0
- stl %r1,%0"
- [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
-
-(define_insn "*movsf_fix"
+(define_insn "*movsf"
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
(match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
- "TARGET_FPREGS && TARGET_FIX
+ "TARGET_FPREGS
&& (register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode))"
"@
@@ -4786,7 +4623,8 @@
stl %r1,%0
itofs %1,%0
ftois %1,%0"
- [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
+ [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")
+ (set_attr "isa" "*,*,*,*,*,*,fix,fix")])
(define_insn "*movsf_nofp"
[(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
@@ -4800,25 +4638,10 @@
stl %r1,%0"
[(set_attr "type" "ilog,ild,ist")])
-(define_insn "*movdf_nofix"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
- (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
- "TARGET_FPREGS && ! TARGET_FIX
- && (register_operand (operands[0], DFmode)
- || reg_or_0_operand (operands[1], DFmode))"
- "@
- cpys %R1,%R1,%0
- ld%- %0,%1
- bis $31,%r1,%0
- ldq %0,%1
- st%- %R1,%0
- stq %r1,%0"
- [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
-
-(define_insn "*movdf_fix"
+(define_insn "*movdf"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
(match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
- "TARGET_FPREGS && TARGET_FIX
+ "TARGET_FPREGS
&& (register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))"
"@
@@ -4830,7 +4653,8 @@
stq %r1,%0
itoft %1,%0
ftoit %1,%0"
- [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
+ [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")
+ (set_attr "isa" "*,*,*,*,*,*,fix,fix")])
(define_insn "*movdf_nofp"
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
@@ -4891,83 +4715,46 @@
})
(define_insn "*movsi"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
- (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ"))]
- "TARGET_ABI_OSF
- && (register_operand (operands[0], SImode)
- || reg_or_0_operand (operands[1], SImode))"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,r")
+ (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ,s"))]
+ "register_operand (operands[0], SImode)
+ || reg_or_0_operand (operands[1], SImode)"
"@
bis $31,%r1,%0
lda %0,%1($31)
ldah %0,%h1($31)
#
ldl %0,%1
- stl %r1,%0"
- [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist")])
-
-(define_insn "*movsi_nt_vms"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m")
- (match_operand:SI 1 "input_operand" "rJ,K,L,s,n,m,rJ"))]
- "TARGET_ABI_OPEN_VMS
- && (register_operand (operands[0], SImode)
- || reg_or_0_operand (operands[1], SImode))"
- "@
- bis $31,%1,%0
- lda %0,%1
- ldah %0,%h1
- lda %0,%1
- #
- ldl %0,%1
- stl %r1,%0"
- [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist")])
-
-(define_insn "*movhi_nobwx"
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (match_operand:HI 1 "input_operand" "rJ,n"))]
- "! TARGET_BWX
- && (register_operand (operands[0], HImode)
- || register_operand (operands[1], HImode))"
- "@
- bis $31,%r1,%0
- lda %0,%L1($31)"
- [(set_attr "type" "ilog,iadd")])
+ stl %r1,%0
+ lda %0,%1"
+ [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist,ldsym")
+ (set_attr "isa" "*,*,*,*,*,*,vms")])
-(define_insn "*movhi_bwx"
+(define_insn "*movhi"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
(match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
- "TARGET_BWX
- && (register_operand (operands[0], HImode)
- || reg_or_0_operand (operands[1], HImode))"
+ "register_operand (operands[0], HImode)
+ || reg_or_0_operand (operands[1], HImode)"
"@
bis $31,%r1,%0
lda %0,%L1($31)
ldwu %0,%1
stw %r1,%0"
- [(set_attr "type" "ilog,iadd,ild,ist")])
+ [(set_attr "type" "ilog,iadd,ild,ist")
+ (set_attr "isa" "*,*,bwx,bwx")])
-(define_insn "*movqi_nobwx"
- [(set (match_operand:QI 0 "register_operand" "=r,r")
- (match_operand:QI 1 "input_operand" "rJ,n"))]
- "! TARGET_BWX
- && (register_operand (operands[0], QImode)
- || register_operand (operands[1], QImode))"
- "@
- bis $31,%r1,%0
- lda %0,%L1($31)"
- [(set_attr "type" "ilog,iadd")])
-
-(define_insn "*movqi_bwx"
+(define_insn "*movqi"
[(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
(match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
- "TARGET_BWX
- && (register_operand (operands[0], QImode)
- || reg_or_0_operand (operands[1], QImode))"
+ "register_operand (operands[0], QImode)
+ || reg_or_0_operand (operands[1], QImode)"
"@
bis $31,%r1,%0
lda %0,%L1($31)
ldbu %0,%1
stb %r1,%0"
- [(set_attr "type" "ilog,iadd,ild,ist")])
+ [(set_attr "type" "ilog,iadd,ild,ist")
+ (set_attr "isa" "*,*,bwx,bwx")])
;; We do two major things here: handle mem->mem and construct long
;; constants.
@@ -5714,7 +5501,7 @@
[(parallel [(match_operand:RELOAD12 0 "any_memory_operand" "=m")
(match_operand:RELOAD12 1 "register_operand" "r")
(match_operand:TI 2 "register_operand" "=&r")])]
- "! TARGET_BWX"
+ "!TARGET_BWX"
{
unsigned regno = REGNO (operands[2]);
@@ -5825,9 +5612,8 @@
(define_insn "*mov<mode>_fix"
[(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f")
(match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))]
- "TARGET_FIX
- && (register_operand (operands[0], <MODE>mode)
- || reg_or_0_operand (operands[1], <MODE>mode))"
+ "register_operand (operands[0], <MODE>mode)
+ || reg_or_0_operand (operands[1], <MODE>mode)"
"@
bis $31,%r1,%0
#
@@ -5838,23 +5624,8 @@
stt %R1,%0
ftoit %1,%0
itoft %1,%0"
- [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
-
-(define_insn "*mov<mode>_nofix"
- [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m")
- (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f"))]
- "! TARGET_FIX
- && (register_operand (operands[0], <MODE>mode)
- || reg_or_0_operand (operands[1], <MODE>mode))"
- "@
- bis $31,%r1,%0
- #
- ldq %0,%1
- stq %r1,%0
- cpys %R1,%R1,%0
- ldt %0,%1
- stt %R1,%0"
- [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst")])
+ [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")
+ (set_attr "isa" "*,*,*,*,*,*,*,fix,fix")])
(define_insn "uminv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=r")
+2011-02-24 Richard Henderson <[email protected]>
+
+ * config/alpha/predicates.md (input_operand): Revert last change;
+ update comment to mention 32-bit VMS rather than Windows.
+
diff --git a/gcc/config/alpha/predicates.md b/gcc/config/alpha/predicates.md
index 9514b8a..da76d4f 100644
--- a/gcc/config/alpha/predicates.md
+++ b/gcc/config/alpha/predicates.md
@@ -195,7 +195,8 @@
|| gotdtp_symbolic_operand (op, mode)
|| gottp_symbolic_operand (op, mode));
}
- return mode == Pmode;
+ /* VMS still has a 32-bit mode. */
+ return mode == ptr_mode || mode == Pmode;
case HIGH:
return (TARGET_EXPLICIT_RELOCS
