Hi all,
Sorry for the rototill, but this bugged me ;)
Since now we have a separate .md file for Thumb1 patterns, I think this
comment is better placed there.
Applied as obvious with r219755.
Thanks,
Kyrill
2015-01-16 Kyrylo Tkachov kyrylo.tkac...@arm.com
* config/arm/arm.md: Move comment about splitting Thumb1 patterns to...
* config/arm/thumb1.md: ... Here.
commit 98c0b0bc525f11407516ced25c8eb7d12c7da1fd
Author: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
Date: Mon Jan 12 13:51:40 2015 +0000
[ARM] Move comment on Thumb1 splitting to thumb1.md
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index bbefb93..79fd0c6 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -22,25 +22,6 @@
;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-;; Beware of splitting Thumb1 patterns that output multiple
-;; assembly instructions, in particular instruction such as SBC and
-;; ADC which consume flags. For example, in the pattern thumb_subdi3
-;; below, the output SUB implicitly sets the flags (assembled to SUBS)
-;; and then the Carry flag is used by SBC to compute the correct
-;; result. If we split thumb_subdi3 pattern into two separate RTL
-;; insns (using define_insn_and_split), the scheduler might place
-;; other RTL insns between SUB and SBC, possibly modifying the Carry
-;; flag used by SBC. This might happen because most Thumb1 patterns
-;; for flag-setting instructions do not have explicit RTL for setting
-;; or clobbering the flags. Instead, they have the attribute "conds"
-;; with value "set" or "clob". However, this attribute is not used to
-;; identify dependencies and therefore the scheduler might reorder
-;; these instruction. Currenly, this problem cannot happen because
-;; there are no separate Thumb1 patterns for individual instruction
-;; that consume flags (except conditional execution, which is treated
-;; differently). In particular there is no Thumb1 armv6-m pattern for
-;; sbc or adc.
-
;;---------------------------------------------------------------------------
;; Constants
diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md
index ff423d8..b1a5897 100644
--- a/gcc/config/arm/thumb1.md
+++ b/gcc/config/arm/thumb1.md
@@ -22,6 +22,27 @@
;; Insn patterns
;;
+;; Beware of splitting Thumb1 patterns that output multiple
+;; assembly instructions, in particular instruction such as SBC and
+;; ADC which consume flags. For example, in the pattern thumb_subdi3
+;; below, the output SUB implicitly sets the flags (assembled to SUBS)
+;; and then the Carry flag is used by SBC to compute the correct
+;; result. If we split thumb_subdi3 pattern into two separate RTL
+;; insns (using define_insn_and_split), the scheduler might place
+;; other RTL insns between SUB and SBC, possibly modifying the Carry
+;; flag used by SBC. This might happen because most Thumb1 patterns
+;; for flag-setting instructions do not have explicit RTL for setting
+;; or clobbering the flags. Instead, they have the attribute "conds"
+;; with value "set" or "clob". However, this attribute is not used to
+;; identify dependencies and therefore the scheduler might reorder
+;; these instruction. Currenly, this problem cannot happen because
+;; there are no separate Thumb1 patterns for individual instruction
+;; that consume flags (except conditional execution, which is treated
+;; differently). In particular there is no Thumb1 armv6-m pattern for
+;; sbc or adc.
+
+
+
(define_insn "*thumb1_adddi3"
[(set (match_operand:DI 0 "register_operand" "=l")
(plus:DI (match_operand:DI 1 "register_operand" "%0")
