After the change to combine, we no longer need all the special-case
patterns.
Tested on powerpc64-linux, as usual. As mentioned with the combine
patch, there are no differences to generated code in cc1.
This does not delete DImode lshiftrt patterns, because those do not
exist (yet).
Is this okay for trunk?
Segher
[ Save the planet! Delete 11% of your machine descriptions! ]
2015-05-10 Segher Boessenkool <seg...@kernel.crashing.org>
* config/rs6000/rs6000.md (extzv): FAIL for SImode.
(extzvsi_internal, *extzvsi_internal1, *extzvsi_internal2,
*rotlsi3_internal7le, *rotlsi3_internal7be, *rotlsi3_internal8le,
*rotlsi3_internal8be, *rotlsi3_internal9le, *rotlsi3_internal9be,
*rotlsi3_internal10le, *rotlsi3_internal10be, *rotlsi3_internal11le,
*rotlsi3_internal11be, *rotlsi3_internal12le, *rotlsi3_internal12be,
*lshiftrt_internal1le, *lshiftrt_internal1be, *lshiftrt_internal2le,
*lshiftrt_internal2be, *lshiftrt_internal3le, *lshiftrt_internal3be,
*lshiftrt_internal4le, *lshiftrt_internal4be, *lshiftrt_internal5le,
*lshiftrt_internal5be, *lshiftrt_internal5le, *lshiftrt_internal5be,
*rotldi3_internal7le, *rotldi3_internal7be, *rotldi3_internal8le,
*rotldi3_internal8be, *rotldi3_internal9le, *rotldi3_internal9be,
*rotldi3_internal10le, *rotldi3_internal10be, *rotldi3_internal11le,
*rotldi3_internal11be, *rotldi3_internal12le, *rotldi3_internal12be,
*rotldi3_internal13le, *rotldi3_internal13be, *rotldi3_internal14le,
*rotldi3_internal14be, *rotldi3_internal15le, *rotldi3_internal15be,
and 30 corresponding splitters): Delete.
---
gcc/config/rs6000/rs6000.md | 1285 +------------------------------------------
1 file changed, 6 insertions(+), 1279 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 4bd16ee..d3b1a7a 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3604,141 +3604,11 @@ (define_expand "extzv"
emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
operands[3]));
else
- emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
- operands[3]));
+ FAIL;
+
DONE;
}")
-(define_insn "extzvsi_internal"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "const_int_operand" "i")
- (match_operand:SI 3 "const_int_operand" "i")))]
- ""
- "*
-{
- int start = INTVAL (operands[3]) & 31;
- int size = INTVAL (operands[2]) & 31;
-
- if (start + size >= 32)
- operands[3] = const0_rtx;
- else
- operands[3] = GEN_INT (start + size);
- return \"rlwinm %0,%1,%3,%s2,31\";
-}"
- [(set_attr "type" "shift")])
-
-(define_insn "*extzvsi_internal1"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand"
"r,r")
- (match_operand:SI 2 "const_int_operand" "i,i")
- (match_operand:SI 3 "const_int_operand" "i,i"))
- (const_int 0)))
- (clobber (match_scratch:SI 4 "=r,r"))]
- ""
- "*
-{
- int start = INTVAL (operands[3]) & 31;
- int size = INTVAL (operands[2]) & 31;
-
- /* Force split for non-cc0 compare. */
- if (which_alternative == 1)
- return \"#\";
-
- /* If the bit-field being tested fits in the upper or lower half of a
- word, it is possible to use andiu. or andil. to test it. This is
- useful because the condition register set-use delay is smaller for
- andi[ul]. than for rlinm. This doesn't work when the starting bit
- position is 0 because the LT and GT bits may be set wrong. */
-
- if ((start > 0 && start + size <= 16) || start >= 16)
- {
- operands[3] = GEN_INT (((1 << (16 - (start & 15)))
- - (1 << (16 - (start & 15) - size))));
- if (start < 16)
- return \"andis. %4,%1,%3\";
- else
- return \"andi. %4,%1,%3\";
- }
-
- if (start + size >= 32)
- operands[3] = const0_rtx;
- else
- operands[3] = GEN_INT (start + size);
- return \"rlwinm. %4,%1,%3,%s2,31\";
-}"
- [(set_attr "type" "shift")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "const_int_operand" "")
- (match_operand:SI 3 "const_int_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 4 ""))]
- "reload_completed"
- [(set (match_dup 4)
- (zero_extract:SI (match_dup 1) (match_dup 2)
- (match_dup 3)))
- (set (match_dup 0)
- (compare:CC (match_dup 4)
- (const_int 0)))]
- "")
-
-(define_insn "*extzvsi_internal2"
- [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand"
"r,r")
- (match_operand:SI 2 "const_int_operand" "i,i")
- (match_operand:SI 3 "const_int_operand" "i,i"))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
- ""
- "*
-{
- int start = INTVAL (operands[3]) & 31;
- int size = INTVAL (operands[2]) & 31;
-
- /* Force split for non-cc0 compare. */
- if (which_alternative == 1)
- return \"#\";
-
- /* Since we are using the output value, we can't ignore any need for
- a shift. The bit-field must end at the LSB. */
- if (start >= 16 && start + size == 32)
- {
- operands[3] = GEN_INT ((1 << size) - 1);
- return \"andi. %0,%1,%3\";
- }
-
- if (start + size >= 32)
- operands[3] = const0_rtx;
- else
- operands[3] = GEN_INT (start + size);
- return \"rlwinm. %0,%1,%3,%s2,31\";
-}"
- [(set_attr "type" "shift")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "const_int_operand" "")
- (match_operand:SI 3 "const_int_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
- "reload_completed"
- [(set (match_dup 0)
- (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
(define_insn "extzvdi_internal"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
@@ -3955,336 +3825,6 @@ (define_split
(const_int 0)))]
"")
-(define_insn "*rotlsi3_internal7le"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extend:SI
- (subreg:QI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
- "!BYTES_BIG_ENDIAN"
- "rlw%I2nm %0,%1,%h2,0xff"
- [(set (attr "cell_micro")
- (if_then_else (match_operand:SI 2 "const_int_operand" "")
- (const_string "not")
- (const_string "always")))
- (set_attr "type" "shift")])
-
-(define_insn "*rotlsi3_internal7be"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extend:SI
- (subreg:QI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
- "BYTES_BIG_ENDIAN"
- "rlw%I2nm %0,%1,%h2,0xff"
- [(set (attr "cell_micro")
- (if_then_else (match_operand:SI 2 "const_int_operand" "")
- (const_string "not")
- (const_string "always")))
- (set_attr "type" "shift")])
-
-(define_insn "*rotlsi3_internal8le"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:SI
- (subreg:QI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand"
"rn,rn")) 0))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "!BYTES_BIG_ENDIAN"
- "@
- rlw%I2nm. %3,%1,%h2,0xff
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*rotlsi3_internal8be"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:SI
- (subreg:QI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand"
"rn,rn")) 3))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "BYTES_BIG_ENDIAN"
- "@
- rlw%I2nm. %3,%1,%h2,0xff
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:SI
- (subreg:QI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
0))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "!BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:SI (subreg:QI
- (rotate:SI (match_dup 1)
- (match_dup 2)) 0)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:SI
- (subreg:QI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
3))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:SI (subreg:QI
- (rotate:SI (match_dup 1)
- (match_dup 2)) 3)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*rotlsi3_internal9le"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:SI
- (subreg:QI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand"
"rn,rn")) 0))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
- "!BYTES_BIG_ENDIAN"
- "@
- rlw%I2nm. %0,%1,%h2,0xff
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*rotlsi3_internal9be"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:SI
- (subreg:QI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand"
"rn,rn")) 3))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
- "BYTES_BIG_ENDIAN"
- "@
- rlw%I2nm. %0,%1,%h2,0xff
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:SI
- (subreg:QI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
0))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
- "!BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:SI
- (subreg:QI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
3))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
- "BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*rotlsi3_internal10le"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extend:SI
- (subreg:HI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_cint_operand" "rn")) 0)))]
- "!BYTES_BIG_ENDIAN"
- "rlw%I2nm %0,%1,%h2,0xffff"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")])
-
-(define_insn "*rotlsi3_internal10be"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extend:SI
- (subreg:HI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "reg_or_cint_operand" "rn")) 2)))]
- "BYTES_BIG_ENDIAN"
- "rlw%I2nm %0,%1,%h2,0xffff"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")])
-
-(define_insn "*rotlsi3_internal11le"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:SI
- (subreg:HI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand"
"rn,rn")) 0))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "!BYTES_BIG_ENDIAN"
- "@
- rlw%I2nm. %3,%1,%h2,0xffff
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*rotlsi3_internal11be"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:SI
- (subreg:HI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand"
"rn,rn")) 2))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "BYTES_BIG_ENDIAN"
- "@
- rlw%I2nm. %3,%1,%h2,0xffff
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:SI
- (subreg:HI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
0))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "!BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:SI (subreg:HI
- (rotate:SI (match_dup 1)
- (match_dup 2)) 0)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:SI
- (subreg:HI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
2))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:SI (subreg:HI
- (rotate:SI (match_dup 1)
- (match_dup 2)) 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*rotlsi3_internal12le"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:SI
- (subreg:HI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand"
"rn,rn")) 0))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
- "!BYTES_BIG_ENDIAN"
- "@
- rlw%I2nm. %0,%1,%h2,0xffff
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*rotlsi3_internal12be"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:SI
- (subreg:HI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "reg_or_cint_operand"
"rn,rn")) 2))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
- "BYTES_BIG_ENDIAN"
- "@
- rlw%I2nm. %0,%1,%h2,0xffff
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:SI
- (subreg:HI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
0))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
- "!BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:SI
- (subreg:HI
- (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "reg_or_cint_operand" ""))
2))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
- "BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
(define_insn "ashl<mode>3"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
@@ -4566,339 +4106,11 @@ (define_split
(match_operand:SI 3 "mask_operand" ""))
(const_int 0)))
(set (match_operand:SI 0 "gpc_reg_operand" "")
- (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "includes_rshift_p (operands[2], operands[3]) && reload_completed"
- [(set (match_dup 0)
- (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
- (set (match_dup 4)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*lshiftrt_internal1le"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extend:SI
- (subreg:QI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "const_int_operand" "i")) 0)))]
- "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
- "rlwinm %0,%1,%s2,0xff"
- [(set_attr "type" "shift")])
-
-(define_insn "*lshiftrt_internal1be"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extend:SI
- (subreg:QI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "const_int_operand" "i")) 3)))]
- "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
- "rlwinm %0,%1,%s2,0xff"
- [(set_attr "type" "shift")])
-
-(define_insn "*lshiftrt_internal2le"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (zero_extend:SI
- (subreg:QI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "const_int_operand" "i,i")) 0))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
- "@
- rlwinm. %3,%1,%s2,0xff
- #"
- [(set_attr "type" "shift")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*lshiftrt_internal2be"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (zero_extend:SI
- (subreg:QI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "const_int_operand" "i,i")) 3))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
- "@
- rlwinm. %3,%1,%s2,0xff
- #"
- [(set_attr "type" "shift")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC
- (zero_extend:SI
- (subreg:QI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "const_int_operand" "")) 0))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) &&
reload_completed"
- [(set (match_dup 3)
- (zero_extend:SI (subreg:QI
- (lshiftrt:SI (match_dup 1)
- (match_dup 2)) 0)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC
- (zero_extend:SI
- (subreg:QI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "const_int_operand" "")) 3))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) &&
reload_completed"
- [(set (match_dup 3)
- (zero_extend:SI (subreg:QI
- (lshiftrt:SI (match_dup 1)
- (match_dup 2)) 3)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*lshiftrt_internal3le"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC
- (zero_extend:SI
- (subreg:QI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "const_int_operand" "i,i")) 0))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2))
0)))]
- "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
- "@
- rlwinm. %0,%1,%s2,0xff
- #"
- [(set_attr "type" "shift")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*lshiftrt_internal3be"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC
- (zero_extend:SI
- (subreg:QI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "const_int_operand" "i,i")) 3))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2))
3)))]
- "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
- "@
- rlwinm. %0,%1,%s2,0xff
- #"
- [(set_attr "type" "shift")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC
- (zero_extend:SI
- (subreg:QI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "const_int_operand" "")) 0))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2))
0)))]
- "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) &&
reload_completed"
- [(set (match_dup 0)
- (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2))
0)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC
- (zero_extend:SI
- (subreg:QI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "const_int_operand" "")) 3))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2))
3)))]
- "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) &&
reload_completed"
- [(set (match_dup 0)
- (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2))
3)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*lshiftrt_internal4le"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extend:SI
- (subreg:HI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "const_int_operand" "i")) 0)))]
- "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
- "rlwinm %0,%1,%s2,0xffff"
- [(set_attr "type" "shift")])
-
-(define_insn "*lshiftrt_internal4be"
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
- (zero_extend:SI
- (subreg:HI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
- (match_operand:SI 2 "const_int_operand" "i")) 2)))]
- "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
- "rlwinm %0,%1,%s2,0xffff"
- [(set_attr "type" "shift")])
-
-(define_insn "*lshiftrt_internal5le"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (zero_extend:SI
- (subreg:HI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "const_int_operand" "i,i")) 0))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
- "@
- rlwinm. %3,%1,%s2,0xffff
- #"
- [(set_attr "type" "shift")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*lshiftrt_internal5be"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC
- (zero_extend:SI
- (subreg:HI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "const_int_operand" "i,i")) 2))
- (const_int 0)))
- (clobber (match_scratch:SI 3 "=r,r"))]
- "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
- "@
- rlwinm. %3,%1,%s2,0xffff
- #"
- [(set_attr "type" "shift")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC
- (zero_extend:SI
- (subreg:HI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "const_int_operand" "")) 0))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) &&
reload_completed"
- [(set (match_dup 3)
- (zero_extend:SI (subreg:HI
- (lshiftrt:SI (match_dup 1)
- (match_dup 2)) 0)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC
- (zero_extend:SI
- (subreg:HI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "const_int_operand" "")) 2))
- (const_int 0)))
- (clobber (match_scratch:SI 3 ""))]
- "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) &&
reload_completed"
- [(set (match_dup 3)
- (zero_extend:SI (subreg:HI
- (lshiftrt:SI (match_dup 1)
- (match_dup 2)) 2)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*lshiftrt_internal5le"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC
- (zero_extend:SI
- (subreg:HI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "const_int_operand" "i,i")) 0))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2))
0)))]
- "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
- "@
- rlwinm. %0,%1,%s2,0xffff
- #"
- [(set_attr "type" "shift")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*lshiftrt_internal5be"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC
- (zero_extend:SI
- (subreg:HI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
- (match_operand:SI 2 "const_int_operand" "i,i")) 2))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2))
2)))]
- "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
- "@
- rlwinm. %0,%1,%s2,0xffff
- #"
- [(set_attr "type" "shift")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC
- (zero_extend:SI
- (subreg:HI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "const_int_operand" "")) 0))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2))
0)))]
- "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) &&
reload_completed"
- [(set (match_dup 0)
- (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2))
0)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC
- (zero_extend:SI
- (subreg:HI
- (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (match_operand:SI 2 "const_int_operand" "")) 2))
- (const_int 0)))
- (set (match_operand:SI 0 "gpc_reg_operand" "")
- (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2))
2)))]
- "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) &&
reload_completed"
+ (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
+ "includes_rshift_p (operands[2], operands[3]) && reload_completed"
[(set (match_dup 0)
- (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2))
2)))
- (set (match_dup 3)
+ (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
+ (set (match_dup 4)
(compare:CC (match_dup 0)
(const_int 0)))]
"")
@@ -6682,491 +5894,6 @@ (define_split
(const_int 0)))]
"")
-(define_insn "*rotldi3_internal7le"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
- "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
- "rld%I2cl %0,%1,%H2,56"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")])
-
-(define_insn "*rotldi3_internal7be"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn")) 7)))]
- "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
- "rld%I2cl %0,%1,%H2,56"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")])
-
-(define_insn "*rotldi3_internal8le"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand"
"rn,rn")) 0))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r"))]
- "TARGET_64BIT && !BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %3,%1,%H2,56
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*rotldi3_internal8be"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand"
"rn,rn")) 7))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r"))]
- "TARGET_64BIT && BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %3,%1,%H2,56
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" ""))
0))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:DI (subreg:QI
- (rotate:DI (match_dup 1)
- (match_dup 2)) 0)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" ""))
7))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:DI (subreg:QI
- (rotate:DI (match_dup 1)
- (match_dup 2)) 7)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*rotldi3_internal9le"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand"
"rn,rn")) 0))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
- "TARGET_64BIT && !BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %0,%1,%H2,56
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*rotldi3_internal9be"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand"
"rn,rn")) 7))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
- "TARGET_64BIT && BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %0,%1,%H2,56
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" ""))
0))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
- "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:QI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" ""))
7))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
- "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*rotldi3_internal10le"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
- "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
- "rld%I2cl %0,%1,%H2,48"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")])
-
-(define_insn "*rotldi3_internal10be"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn")) 6)))]
- "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
- "rld%I2cl %0,%1,%H2,48"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")])
-
-(define_insn "*rotldi3_internal11le"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand"
"rn,rn")) 0))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r"))]
- "TARGET_64BIT && !BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %3,%1,%H2,48
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*rotldi3_internal11be"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand"
"rn,rn")) 6))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r"))]
- "TARGET_64BIT && BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %3,%1,%H2,48
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" ""))
0))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:DI (subreg:HI
- (rotate:DI (match_dup 1)
- (match_dup 2)) 0)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" ""))
6))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:DI (subreg:HI
- (rotate:DI (match_dup 1)
- (match_dup 2)) 6)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*rotldi3_internal12le"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand"
"rn,rn")) 0))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
- "TARGET_64BIT && !BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %0,%1,%H2,48
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*rotldi3_internal12be"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand"
"rn,rn")) 6))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
- "TARGET_64BIT && BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %0,%1,%H2,48
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" ""))
0))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
- "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:HI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" ""))
6))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
- "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "*rotldi3_internal13le"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (zero_extend:DI
- (subreg:SI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn")) 0)))]
- "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
- "rld%I2cl %0,%1,%H2,32"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")])
-
-(define_insn "*rotldi3_internal13be"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (zero_extend:DI
- (subreg:SI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
- (match_operand:DI 2 "reg_or_cint_operand" "rn")) 4)))]
- "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
- "rld%I2cl %0,%1,%H2,32"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")])
-
-(define_insn "*rotldi3_internal14le"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:SI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand"
"rn,rn")) 0))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r"))]
- "TARGET_64BIT && !BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %3,%1,%H2,32
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*rotldi3_internal14be"
- [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:SI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand"
"rn,rn")) 4))
- (const_int 0)))
- (clobber (match_scratch:DI 3 "=r,r"))]
- "TARGET_64BIT && BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %3,%1,%H2,32
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:SI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" ""))
0))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:DI (subreg:SI
- (rotate:DI (match_dup 1)
- (match_dup 2)) 0)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:SI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" ""))
4))
- (const_int 0)))
- (clobber (match_scratch:DI 3 ""))]
- "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 3)
- (zero_extend:DI (subreg:SI
- (rotate:DI (match_dup 1)
- (match_dup 2)) 4)))
- (set (match_dup 0)
- (compare:CC (match_dup 3)
- (const_int 0)))]
- "")
-
-(define_insn "*rotldi3_internal15le"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:SI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand"
"rn,rn")) 0))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
- "TARGET_64BIT && !BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %0,%1,%H2,32
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_insn "*rotldi3_internal15be"
- [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
- (compare:CC (zero_extend:DI
- (subreg:SI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
- (match_operand:DI 2 "reg_or_cint_operand"
"rn,rn")) 4))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
- (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
- "TARGET_64BIT && BYTES_BIG_ENDIAN"
- "@
- rld%I2cl. %0,%1,%H2,32
- #"
- [(set_attr "type" "shift")
- (set_attr "maybe_var_shift" "yes")
- (set_attr "dot" "yes")
- (set_attr "length" "4,8")])
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:SI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" ""))
0))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
- "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_split
- [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (zero_extend:DI
- (subreg:SI
- (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
- (match_operand:DI 2 "reg_or_cint_operand" ""))
4))
- (const_int 0)))
- (set (match_operand:DI 0 "gpc_reg_operand" "")
- (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
- "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
- [(set (match_dup 0)
- (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
- (set (match_dup 3)
- (compare:CC (match_dup 0)
- (const_int 0)))]
- "")
(define_insn "*ashldi3_internal4"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
--
1.8.1.4
