Hi all,
This patch transforms the Cortex-A53 erratum 835769 workaround checks into a
macro.
This way we don't have to override aarch64_fix_a53_err835769 in the default case
and this allows us to keep track of when the user doesn't specify this option,
which may come in handy later on when we decide the inlining rules.
This patch also makes TARGET_FIX_ERR_A53_835769_DEFAULT unconditionally defined
to
0 or 1, so that we don't have to check it if #ifdefs.
Bootstrapped and tested as part of series on aarch64.
Checked that the workaround is applied as previously.
Ok for trunk?
2015-07-16 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* config/aarch64/aarch64.h (TARGET_FIX_ERR_A53_835769_DEFAULT): Always
define to 0 or 1.
(TARGET_FIX_ERR_A53_835769): New macro.
* config/aarch64/aarch64.c (aarch64_override_options_internal): Remove
handling of opts->x_aarch64_fix_a53_err835769.
(aarch64_madd_needs_nop): Check for TARGET_FIX_ERR_A53_835769 rather
than aarch64_fix_a53_err835769.
* config/aarch64/aarch64-elf-raw.h: Update for above changes.
* config/aarch64/aarch64-linux.h: Likewise.
commit 12e50e9fdcb86b0a4c73b3b43d92c386e9504637
Author: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
Date: Thu May 21 09:49:12 2015 +0100
[AArch64][4/N] Create TARGET_FIX_ERR_A53_835769 and use that instead of aarch64_fix_a53_err835769
diff --git a/gcc/config/aarch64/aarch64-elf-raw.h b/gcc/config/aarch64/aarch64-elf-raw.h
index bd5e51c..66b4c8b 100644
--- a/gcc/config/aarch64/aarch64-elf-raw.h
+++ b/gcc/config/aarch64/aarch64-elf-raw.h
@@ -27,7 +27,7 @@
" crtend%O%s crtn%O%s " \
"%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s}"
-#ifdef TARGET_FIX_ERR_A53_835769_DEFAULT
+#if TARGET_FIX_ERR_A53_835769_DEFAULT
#define CA53_ERR_835769_SPEC \
" %{!mno-fix-cortex-a53-835769:--fix-cortex-a53-835769}"
#else
diff --git a/gcc/config/aarch64/aarch64-linux.h b/gcc/config/aarch64/aarch64-linux.h
index 1600a32..b9d7805 100644
--- a/gcc/config/aarch64/aarch64-linux.h
+++ b/gcc/config/aarch64/aarch64-linux.h
@@ -52,7 +52,7 @@
" %{mfix-cortex-a53-835769:--fix-cortex-a53-835769}"
#endif
-#ifdef TARGET_FIX_ERR_A53_843419_DEFAULT
+#if TARGET_FIX_ERR_A53_843419_DEFAULT
#define CA53_ERR_843419_SPEC \
" %{!mno-fix-cortex-a53-843419:--fix-cortex-a53-843419}"
#else
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 5ea65e3..aff23d6 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -7552,15 +7552,6 @@ aarch64_override_options_internal (struct gcc_options *opts)
if (opts->x_flag_strict_volatile_bitfields < 0 && abi_version_at_least (2))
opts->x_flag_strict_volatile_bitfields = 1;
- if (opts->x_aarch64_fix_a53_err835769 == 2)
- {
-#ifdef TARGET_FIX_ERR_A53_835769_DEFAULT
- opts->x_aarch64_fix_a53_err835769 = 1;
-#else
- opts->x_aarch64_fix_a53_err835769 = 0;
-#endif
- }
-
/* -mgeneral-regs-only sets a mask in target_flags, make sure that
aarch64_isa_flags does not contain the FP/SIMD/Crypto feature flags
in case some code tries reading aarch64_isa_flags directly to check if
@@ -9004,7 +8995,7 @@ aarch64_madd_needs_nop (rtx_insn* insn)
rtx_insn *prev;
rtx body;
- if (!aarch64_fix_a53_err835769)
+ if (!TARGET_FIX_ERR_A53_835769)
return false;
if (recog_memoized (insn) < 0)
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 2a097af..d2d1ebf 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -233,6 +233,20 @@ extern unsigned long aarch64_isa_flags;
/* CRC instructions that can be enabled through +crc arch extension. */
#define TARGET_CRC32 (AARCH64_ISA_CRC)
+/* Make sure this is always defined so we don't have to check for ifdefs
+ but rather use normal ifs. */
+#ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
+#define TARGET_FIX_ERR_A53_835769_DEFAULT 0
+#else
+#undef TARGET_FIX_ERR_A53_835769_DEFAULT
+#define TARGET_FIX_ERR_A53_835769_DEFAULT 1
+#endif
+
+/* Apply the workaround for Cortex-A53 erratum 835769. */
+#define TARGET_FIX_ERR_A53_835769 \
+ ((aarch64_fix_a53_err835769 == 2) \
+ ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769)
+
/* Standard register usage. */
/* 31 64-bit general purpose registers R0-R30:
