2011/7/26 Richard Sandiford <richard.sandif...@linaro.org>: > Note that on ARM, the comparison and loop counter addition can happen > as a single parallel:
Certainly, I notice such "subs" ARM instructions. IMHO, this pattern seems to appear rarely in real loops. For loops without doloop_end pattern we have to make the following instruction transformation as I have noticed already: "The final register value X in compare instruction regF=COMPARE(regC,X) is changed to another value Y respective to the stage this instruction is scheduled: (Y = X - stage * step)" In subs instruction we are unable to do this, because we can't change the number to compare with. It seems there are three following ways of solving this. The first way is to check that counter register is not used by non-control-flow instructions before running SMS on such loops. The same condition is checked in doloop_condition_get. The second way is to allow SMS to process loop with subs instruction, but when the schedule is already computed, then allow to apply it only if X == Y (otherwise new schedule lead to miscompilation). The third way is to create a pair of sub and cmp instructions instead of subs when needed. > I think we'd need to handle that too before getting rid of the > ARM doloop_end pattern. I think all three ways are complicated enough and decide to begin with implementing SMS without such loops support. -- Roman Zhuykov zhr...@ispras.ru
