On Mon, Sep 28, 2015 at 4:52 PM, Evandro Menezes <e.mene...@samsung.com> wrote:
> In some micro-architectures the insns to load or store pairs of vector
> registers are implemented rather differently from those affecting lanes in
> vector registers. Then, it's important that such insns be described
> likewise differently in the scheduling model.
>
> This patch adds the insn types neon_ldp{,_q} and neon_stp{,_q} apart from
> the current neon_load2_2reg_q and neon_store2_2reg_q types, respectively.
This is a very useful patch for the ThunderX core also. I will update
the config/aarch64/thunderx.md file if this patch gets approved.
Thanks,
Andrew
>
> Thank you,
>
> --
> Evandro Menezes
>
