Hi all,
As part of the SWITCHABLE_TARGET work I inadvertently changed the behaviour of
-mgeneral-regs-only with respect to the .arch directives that we emit.
The behaviour of -mgeneral-regs-only in GCC 5 and earlier is such that it
disallows the usage of FP/SIMD registers but does *not* stop the compiler from
emitting the +fp,+simd etc extensions in the .arch directive of the generated
assembly. This is to accommodate users who may want to write inline assembly
in a file compiled with -mgeneral-regs-only.
This patch restores the trunk behaviour in that respect to that of GCC 5 and
the documentation for the option is tweaked a bit to reflect that.
Bootstrapped and tested on aarch64.
Ok for trunk?
Thanks,
Kyrill
2015-10-01 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* config/aarch64/aarch64.c (aarch64_override_options_internal):
Do not alter target_flags due to TARGET_GENERAL_REGS_ONLY_P.
* doc/invoke.texi (AArch64 options): Mention that -mgeneral-regs-only
does not affect the assembler directives.
2015-10-01 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* gcc.target/aarch64/mgeneral-regs_4.c: New test.
commit bd99347f0dad9346dc16ffc13cd423a4889ae339
Author: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
Date: Fri Sep 11 09:40:44 2015 +0100
[AArch64] Don't allow -mgeneral-regs-only to change the .arch assembler directives
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 115c3a7..81e0eb0 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -7658,19 +7658,6 @@ aarch64_override_options_internal (struct gcc_options *opts)
if (opts->x_flag_strict_volatile_bitfields < 0 && abi_version_at_least (2))
opts->x_flag_strict_volatile_bitfields = 1;
- /* -mgeneral-regs-only sets a mask in target_flags, make sure that
- aarch64_isa_flags does not contain the FP/SIMD/Crypto feature flags
- in case some code tries reading aarch64_isa_flags directly to check if
- FP is available. Reuse the aarch64_parse_extension machinery since it
- knows how to disable any other flags that fp implies. */
- if (TARGET_GENERAL_REGS_ONLY_P (opts->x_target_flags))
- {
- /* aarch64_parse_extension takes char* rather than const char* because
- it is usually called from within other parsing functions. */
- char tmp_str[] = "+nofp";
- aarch64_parse_extension (tmp_str, &opts->x_aarch64_isa_flags);
- }
-
initialize_aarch64_code_model (opts);
initialize_aarch64_tls_size (opts);
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 547ee2d..e8067f2 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12304,10 +12304,9 @@ Generate big-endian code. This is the default when GCC is configured for an
@item -mgeneral-regs-only
@opindex mgeneral-regs-only
-Generate code which uses only the general-purpose registers. This is equivalent
-to feature modifier @option{nofp} of @option{-march} or @option{-mcpu}, except
-that @option{-mgeneral-regs-only} takes precedence over any conflicting feature
-modifier regardless of sequence.
+Generate code which uses only the general-purpose registers. This will prevent
+the compiler from using floating-point and Advanced SIMD registers but will not
+impose any restrictions on the assembler.
@item -mlittle-endian
@opindex mlittle-endian
diff --git a/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_4.c b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_4.c
new file mode 100644
index 0000000..8eb50aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mgeneral-regs_4.c
@@ -0,0 +1,9 @@
+/* { dg-options "-mgeneral-regs-only -march=armv8-a+simd+fp -O2" } */
+
+int
+test (void)
+{
+ return 1;
+}
+
+/* { dg-final { scan-assembler "\.arch.*fp.*simd" } } */
