Ping. https://gcc.gnu.org/ml/gcc-patches/2015-11/msg01392.html
Thanks, Kyrill On 11/11/15 16:10, Kyrill Tkachov wrote:
Hi all, The attached testcase ICEs when compiled with -march=armv6k -mthumb -Os or any march for which -mthumb gives Thumb1: error: unrecognizable insn: } ^ (insn 13 12 14 5 (set (reg:SI 116 [ x ]) (unspec:SI [ (mem:SI (reg/v/f:SI 112 [ s ]) [0 MEM[(unsigned char *)s_1(D)]+0 S4 A8]) ] UNSPEC_UNALIGNED_LOAD)) besttry.c:9 -1 (nil)) The problem is that the expands a movmisalign pattern but the resulting unaligned loads don't match any define_insn because they are gated on unaligned_access && TARGET_32BIT. The unaligned_access expander is gated only on unaligned_access. This small patch fixes the issue by turning off unaligned_access if TARGET_32BIT is not true. We can then remove TARGET_32BIT from the unaligned load/store patterns conditions as a cleanup. Bootstrapped and tested on arm-none-linux-gnueabihf. Ok for trunk? Thanks, Kyrill 2015-11-11 Kyrylo Tkachov <kyrylo.tkac...@arm.com> * config/arm/arm.c (arm_option_override): Require TARGET_32BIT for unaligned_access. * config/arm/arm.md (unaligned_loadsi): Remove redundant TARGET_32BIT from matching condition. (unaligned_loadhis): Likewise. (unaligned_loadhiu): Likewise. (unaligned_storesi): Likewise. (unaligned_storehi): Likewise. 2015-11-11 Kyrylo Tkachov <kyrylo.tkac...@arm.com> * gcc.target/arm/armv6-unaligned-load-ice.c: New test.