On Wed, Dec 30, 2015 at 9:53 PM, H.J. Lu <hjl.to...@gmail.com> wrote: > SSE vector arithmetic and logic instructions only accept aligned memory > operand. This patch adds vector_memory_operand and "Bm" constraint for > aligned SSE memory operand. They are applied to SSE any_logic patterns. > > OK for trunk and release branches if there are regressions?
This patch is just papering over deeper problem, as Jakub said in the PR [1]: --q-- GCC uses the ix86_legitimate_combined_insn target hook to disallow misaligned memory into certain SSE instructions. (subreg:V4SI (reg:TI 245 [ MEM[(const struct bitset &)FeatureEntry_21 + 8] ]) 0) is not misaligned memory, it is a subreg of a pseudo register, so it is fine. If the replacement of the pseudo register with memory happens in some other pass, then it probably either should use the legitimate_combined_insn target hook or some other one. I think we have already a PR where that happens during live range shrinking. --/q-- Please figure out where memory replacement happens. There are several other SSE insns (please grep the .md for "ssememalign" attribute) that are affected by this problem, so fixing a couple of patterns won't solve the problem completely. Looks like infrastructure problem to me, targets should have the last say on the validity of the insns. [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68991#c5 Uros.
