Hi all,
The test gcc.target/aarch64/tst_3.c fails for an explicit -mcpu=cortex-a53
because we don't
handle the recent compare with zero_extract pattern properly in rtx costs, so
we end up recursing
into its operands and end up rejecting the combination for some CPUs,
generating an AND-immediate
followed by a comparison against zero, instead of the TST-immediate instruction
expected by the test.
This patch adds handling for that pattern so that we properly handle it the
same ways as an ANDS instruction.
With this patch the aforementioned test passes for -mcpu=cortex-a53 as well.
Bootstrapped and tested on aarch64-none-linux-gnu.
Ok for trunk?
Thanks,
Kyrill
2016-01-11 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs, COMPARE case):
Handle COMPARE of ZERO_EXTRACT against zero form of TST-immediate.
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index a66508a11fe380e9277d1589ce9dc11eef2fe6a3..8fe433f8f1dac836983d57d5c3dde128697dc2d8 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -6490,6 +6490,23 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer ATTRIBUTE_UNUSED,
goto cost_minus;
}
+ if (GET_CODE (op0) == ZERO_EXTRACT && op1 == const0_rtx
+ && GET_MODE (x) == CC_NZmode && CONST_INT_P (XEXP (op0, 1))
+ && CONST_INT_P (XEXP (op0, 2)))
+ {
+ /* COMPARE of ZERO_EXTRACT form of TST-immediate.
+ Handle it here directly rather than going to cost_logic
+ since we know the immediate generated for the TST is valid
+ so we can avoid creating an intermediate rtx for it only
+ for costing purposes. */
+ if (speed)
+ *cost += extra_cost->alu.logical;
+
+ *cost += rtx_cost (XEXP (op0, 0), GET_MODE (op0),
+ ZERO_EXTRACT, 0, speed);
+ return true;
+ }
+
if (GET_CODE (op1) == NEG)
{
/* CMN. */
