Some patterns are using '%w2' for immediate operands, which means that a zero immediate is actually emitted as 'wzr' or 'xzr'. This not only changes an immediate operand into a register operand but may emit illegal instructions from legal RTL (eg. ORR x0, SP, xzr rather than ORR x0, SP, 0).
Remove the fallthrough in aarch64_print_operand from the 'w' and 'x' case into the '0' case that created this issue. Modify a few patterns to use '%2' rather than '%w2' for an immediate or memory operand so they now print correctly without the fallthrough. OK for trunk? (note this requires https://gcc.gnu.org/ml/gcc-patches/2016-04/msg01265.html to be committed first) ChangeLog: 2016-04-22 Wilco Dijkstra <wdijk...@arm.com> gcc/ * config/aarch64/aarch64.md (add<mode>3_compareC_cconly_imm): Remove use of %w for immediate. (add<mode>3_compareC_imm): Likewise. (<optab>si3_uxtw): Split into register and immediate variants. (andsi3_compare0_uxtw): Likewise. (and<mode>3_compare0): Likewise. (and<mode>3nr_compare0): Likewise. (stack_protect_test_<mode>): Don't use %x for memory operands. * config/aarch64/aarch64.c (aarch64_print_operand): Remove fallthrough from 'w' and 'x' case into '0' case. -- diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 881dc52e2de03231abb217a9ce22cbb1cc44bc6c..bcef50825c8315c39e29dbe57c387ea2a4fe445d 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4608,7 +4608,8 @@ aarch64_print_operand (FILE *f, rtx x, int code) break; } - /* Fall through */ + output_operand_lossage ("invalid operand for '%%%c'", code); + return; case 0: /* Print a normal operand, if it's a general register, then we diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 3e474bb0939c5786a181b67173c62ada73c4bd82..60a20366d16fb1d4eccb43ac32cfc1f0e6096cd0 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1779,7 +1779,7 @@ "aarch64_zero_extend_const_eq (<DWI>mode, operands[2], <MODE>mode, operands[1])" "@ - cmn\\t%<w>0, %<w>1 + cmn\\t%<w>0, %1 cmp\\t%<w>0, #%n1" [(set_attr "type" "alus_imm")] ) @@ -1811,7 +1811,7 @@ "aarch64_zero_extend_const_eq (<DWI>mode, operands[3], <MODE>mode, operands[2])" "@ - adds\\t%<w>0, %<w>1, %<w>2 + adds\\t%<w>0, %<w>1, %2 subs\\t%<w>0, %<w>1, #%n2" [(set_attr "type" "alus_imm")] ) @@ -3418,7 +3418,9 @@ (LOGICAL:SI (match_operand:SI 1 "register_operand" "%r,r") (match_operand:SI 2 "aarch64_logical_operand" "r,K"))))] "" - "<logical>\\t%w0, %w1, %w2" + "@ + <logical>\\t%w0, %w1, %w2 + <logical>\\t%w0, %w1, %2" [(set_attr "type" "logic_reg,logic_imm")] ) @@ -3431,7 +3433,9 @@ (set (match_operand:GPI 0 "register_operand" "=r,r") (and:GPI (match_dup 1) (match_dup 2)))] "" - "ands\\t%<w>0, %<w>1, %<w>2" + "@ + ands\\t%<w>0, %<w>1, %<w>2 + ands\\t%<w>0, %<w>1, %2" [(set_attr "type" "logics_reg,logics_imm")] ) @@ -3445,7 +3449,9 @@ (set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))] "" - "ands\\t%w0, %w1, %w2" + "@ + ands\\t%w0, %w1, %w2 + ands\\t%w0, %w1, %2" [(set_attr "type" "logics_reg,logics_imm")] ) @@ -3799,7 +3805,9 @@ (match_operand:GPI 1 "aarch64_logical_operand" "r,<lconst>")) (const_int 0)))] "" - "tst\\t%<w>0, %<w>1" + "@ + tst\\t%<w>0, %<w>1 + tst\\t%<w>0, %1" [(set_attr "type" "logics_reg,logics_imm")] ) @@ -5187,7 +5195,7 @@ UNSPEC_SP_TEST)) (clobber (match_scratch:PTR 3 "=&r"))] "" - "ldr\t%<w>3, %x1\;ldr\t%<w>0, %x2\;eor\t%<w>0, %<w>3, %<w>0" + "ldr\t%<w>3, %1\;ldr\t%<w>0, %2\;eor\t%<w>0, %<w>3, %<w>0" [(set_attr "length" "12") (set_attr "type" "multiple")])