Hi all,
We have a few instances in the arm backend where we take the INTVAL of an RTX
and immediately cast it to
an (unsigned HOST_WIDE_INT). This is exactly equivalent to taking the UINTVAL
of the RTX.
This patch fixes such uses. A couple of uses in arm.md take the INTVAL and then
compare it to the constant
1 which can be replaced by a comparison with CONST1_RTX without extracting the
INTVAL.
Bootstrapped and tested on arm-none-linux-gnueabihf.
Committing as obvious.
Thanks,
Kyrill
2016-05-24 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* config/arm/arm.md (ashldi3): Replace comparison of INTVAL of
operands[2] against 1 with comparison against CONST1_RTX.
(ashrdi3): Likewise.
(lshrdi3): Likewise.
(ashlsi3): Replace cast of INTVAL to unsigned HOST_WIDE_INT with
UINTVAL.
(ashrsi3): Likewise.
(lshrsi3): Likewise.
(rotrsi3): Likewise.
(define_split above *compareqi_eq0): Likewise.
(define_split above "prologue"): Likewise.
* config/arm/arm.c (thumb1_size_rtx_costs): Likewise.
* config/arm/predicates.md (shift_operator): Likewise.
(shift_nomul_operator): Likewise.
(sat_shift_operator): Likewise.
(thumb1_cmp_operand): Likewise.
(const_neon_scalar_shift_amount_operand): Replace manual range
check with IN_RANGE.
* config/arm/thumb1.md (define_peephole2 above *thumb_subdi3):
Replace cast of INTVAL to unsigned HOST_WIDE_INT with UINTVAL.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 78478303593522d186734c452c970fb013bf846e..55b3a82618ef4138573baad3f0654162a33e1032 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -8986,7 +8986,7 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
case CONST_INT:
if (outer == SET)
{
- if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
+ if (UINTVAL (x) < 256)
return COSTS_N_INSNS (1);
/* See split "TARGET_THUMB1 && satisfies_constraint_J". */
if (INTVAL (x) >= -255 && INTVAL (x) <= -1)
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 8c63bf7b75c4e84283ffee471375389f5a5b1a34..e78ede8945fb2d0c0ac5a5af7b96a64d061cf5c3 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -3761,8 +3761,7 @@ (define_expand "ashldi3"
{
rtx scratch1, scratch2;
- if (CONST_INT_P (operands[2])
- && (HOST_WIDE_INT) INTVAL (operands[2]) == 1)
+ if (operands[2] == CONST1_RTX (SImode))
{
emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1]));
DONE;
@@ -3807,7 +3806,7 @@ (define_expand "ashlsi3"
"TARGET_EITHER"
"
if (CONST_INT_P (operands[2])
- && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
+ && (UINTVAL (operands[2])) > 31)
{
emit_insn (gen_movsi (operands[0], const0_rtx));
DONE;
@@ -3835,8 +3834,7 @@ (define_expand "ashrdi3"
{
rtx scratch1, scratch2;
- if (CONST_INT_P (operands[2])
- && (HOST_WIDE_INT) INTVAL (operands[2]) == 1)
+ if (operands[2] == CONST1_RTX (SImode))
{
emit_insn (gen_arm_ashrdi3_1bit (operands[0], operands[1]));
DONE;
@@ -3881,7 +3879,7 @@ (define_expand "ashrsi3"
"TARGET_EITHER"
"
if (CONST_INT_P (operands[2])
- && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
+ && UINTVAL (operands[2]) > 31)
operands[2] = GEN_INT (31);
"
)
@@ -3906,8 +3904,7 @@ (define_expand "lshrdi3"
{
rtx scratch1, scratch2;
- if (CONST_INT_P (operands[2])
- && (HOST_WIDE_INT) INTVAL (operands[2]) == 1)
+ if (operands[2] == CONST1_RTX (SImode))
{
emit_insn (gen_arm_lshrdi3_1bit (operands[0], operands[1]));
DONE;
@@ -3952,7 +3949,7 @@ (define_expand "lshrsi3"
"TARGET_EITHER"
"
if (CONST_INT_P (operands[2])
- && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
+ && (UINTVAL (operands[2])) > 31)
{
emit_insn (gen_movsi (operands[0], const0_rtx));
DONE;
@@ -3986,7 +3983,7 @@ (define_expand "rotrsi3"
if (TARGET_32BIT)
{
if (CONST_INT_P (operands[2])
- && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
+ && UINTVAL (operands[2]) > 31)
operands[2] = GEN_INT (INTVAL (operands[2]) % 32);
}
else /* TARGET_THUMB1 */
@@ -5129,7 +5126,7 @@ (define_split
(match_operator 5 "subreg_lowpart_operator"
[(match_operand:SI 4 "s_register_operand" "")]))))]
"TARGET_32BIT
- && ((unsigned HOST_WIDE_INT) INTVAL (operands[3])
+ && (UINTVAL (operands[3])
== (GET_MODE_MASK (GET_MODE (operands[5]))
& (GET_MODE_MASK (GET_MODE (operands[5]))
<< (INTVAL (operands[2])))))"
@@ -10187,8 +10184,8 @@ (define_split
(match_operand 1 "const_int_operand" "")))
(clobber (match_scratch:SI 2 ""))]
"TARGET_ARM
- && (((unsigned HOST_WIDE_INT) INTVAL (operands[1]))
- == (((unsigned HOST_WIDE_INT) INTVAL (operands[1])) >> 24) << 24)"
+ && ((UINTVAL (operands[1]))
+ == ((UINTVAL (operands[1])) >> 24) << 24)"
[(set (match_dup 2) (zero_extend:SI (match_dup 0)))
(set (reg:CC CC_REGNUM) (compare:CC (match_dup 2) (match_dup 1)))]
"
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index e9d19606cbb05e268db9ac081a51625adfa2436a..86c1bb62ae9ba433afe3169e07055c1b818e26c8 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -178,8 +178,7 @@ (define_predicate "shift_amount_operand"
(define_predicate "const_neon_scalar_shift_amount_operand"
(and (match_code "const_int")
- (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) <= GET_MODE_BITSIZE (mode)
- && ((unsigned HOST_WIDE_INT) INTVAL (op)) > 0")))
+ (match_test "IN_RANGE (UINTVAL (op), 1, GET_MODE_BITSIZE (mode))")))
(define_predicate "ldrd_strd_offset_operand"
(and (match_operand 0 "const_int_operand")
@@ -293,19 +292,19 @@ (define_special_predicate "shift_operator"
(match_test "power_of_two_operand (XEXP (op, 1), mode)"))
(and (match_code "rotate")
(match_test "CONST_INT_P (XEXP (op, 1))
- && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
+ && (UINTVAL (XEXP (op, 1))) < 32")))
(and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
(match_test "!CONST_INT_P (XEXP (op, 1))
- || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
+ || (UINTVAL (XEXP (op, 1))) < 32")))
(match_test "mode == GET_MODE (op)")))
(define_special_predicate "shift_nomul_operator"
(and (ior (and (match_code "rotate")
(match_test "CONST_INT_P (XEXP (op, 1))
- && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32"))
+ && (UINTVAL (XEXP (op, 1))) < 32"))
(and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
(match_test "!CONST_INT_P (XEXP (op, 1))
- || ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
+ || (UINTVAL (XEXP (op, 1))) < 32")))
(match_test "mode == GET_MODE (op)")))
;; True for shift operators which can be used with saturation instructions.
@@ -314,7 +313,7 @@ (define_special_predicate "sat_shift_operator"
(match_test "power_of_two_operand (XEXP (op, 1), mode)"))
(and (match_code "ashift,ashiftrt")
(match_test "CONST_INT_P (XEXP (op, 1))
- && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)")))
+ && (UINTVAL (XEXP (op, 1)) < 32)")))
(match_test "mode == GET_MODE (op)")))
;; True for MULT, to identify which variant of shift_operator is in use.
@@ -540,7 +539,7 @@ (define_predicate "thumb1_cmp_operand"
(ior (and (match_code "reg,subreg")
(match_operand 0 "s_register_operand"))
(and (match_code "const_int")
- (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)) < 256"))))
+ (match_test "(UINTVAL (op)) < 256"))))
(define_predicate "thumb1_cmpneg_operand"
(and (match_code "const_int")
diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md
index 072ed4da47ad164eb406bedc3fccc589ac705e9f..c5b59bd3e1577a904a93bb8bdf7d486b086fb848 100644
--- a/gcc/config/arm/thumb1.md
+++ b/gcc/config/arm/thumb1.md
@@ -114,8 +114,8 @@ (define_peephole2
(set (match_dup 0)
(plus:SI (match_dup 0) (reg:SI SP_REGNUM)))]
"TARGET_THUMB1
- && (unsigned HOST_WIDE_INT) (INTVAL (operands[1])) < 1024
- && (INTVAL (operands[1]) & 3) == 0"
+ && UINTVAL (operands[1]) < 1024
+ && (UINTVAL (operands[1]) & 3) == 0"
[(set (match_dup 0) (plus:SI (reg:SI SP_REGNUM) (match_dup 1)))]
""
)
