This patchset improves zero extend costs and code generation.
When zero extending a 32-bit register, we emit a "mov", but currently
report the cost of the "mov" incorrectly.
In terms of speed, we currently say the cost is that of an extend
operation. But the cost of a "mov" is the cost of 1 instruction, so fix
that.
In terms of size, we currently say that the "mov" takes 0 instructions.
Fix it by changing it to 1.
Bootstrapped and tested on aarch64-none-elf.
2016-07-19 Kristina Martsenko <kristina.martse...@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Fix cost of zero extend.
---
gcc/config/aarch64/aarch64.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index
d4c5665cf4d0b046a6129c35007fc2ae8265812f..bddffc3ab28cde3a996fd13c060de36227315fb5
100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -6430,12 +6430,10 @@ cost_plus:
{
int op_cost = rtx_cost (op0, VOIDmode, ZERO_EXTEND, 0, speed);
- if (!op_cost && speed)
- /* MOV. */
- *cost += extra_cost->alu.extend;
- else
+ if (op_cost)
/* Free, the cost is that of the SI mode operation. */
*cost = op_cost;
+ /* Otherwise MOV. */
return true;
}
--
2.1.4
