On Wed, Jul 27, 2016 at 10:32:21AM -0400, Michael Meissner wrote:
> 2016-07-27 Michael Meissner <[email protected]>
>
> * config/rs6000/vector.md (vec_extract<mode>): Change the calling
> signature of rs6000_expand_vector_extract so that the element
> number is a RTX instead of a constant integer.
> * config/rs6000/rs6000-protos.h (rs6000_expand_vector_extract):
> Likewise.
> * config/rs6000/rs6000.c (rs6000_expand_vector_extract): Likewise.
> (altivec_expand_vec_ext_builtin): Likewise.
> * config/rs6000/altivec.md (reduc_plus_scal_<mode>): Likewise.
> * config/rs6000/vsx.md (vsx_extract_<mode>): Fix spelling of the
> MFVSRLD instruction.
> @@ -14658,14 +14661,18 @@ altivec_expand_vec_ext_builtin (tree exp
> {
> machine_mode tmode, mode0;
> tree arg0, arg1;
> - int elt;
> rtx op0;
> + rtx op1;
You could put op0, op1 on one line, or better yet, declare them where
they are first initialised.
> --- gcc/config/rs6000/vsx.md (revision 238772)
> +++ gcc/config/rs6000/vsx.md (working copy)
> @@ -2159,7 +2159,7 @@ (define_insn "vsx_extract_<mode>"
>
> else if (element == VECTOR_ELEMENT_MFVSRLD_64BIT && INT_REGNO_P (op0_regno)
> && TARGET_P9_VECTOR && TARGET_POWERPC64 && TARGET_DIRECT_MOVE)
> - return "mfvsrdl %0,%x1";
> + return "mfvsrld %0,%x1";
Later patches have some testcases?
This is okay for trunk, with or without the cosmetic change. Thanks,
Segher
