This is necessary when adding shrink-wrapping; otherwise dwarf2cfi sees
inconsistent information and aborts.
Tested on mips64-elf together with the rest of the shrink-wrapping
patches. Ok?
Bernd
* config/mips/mips.c (cfa_restores): New static variable.
(mips_restore_reg): Add to it.
(mips_expand_epilogue): Initialize it. Annotate RTL to ensure
dwarf2cfi sees the effects of the epilogue.
Index: gcc/config/mips/mips.c
===================================================================
--- gcc/config/mips/mips.c (revision 178135)
+++ gcc/config/mips/mips.c (working copy)
@@ -10227,7 +10227,10 @@ mips_expand_prologue (void)
emit_insn (gen_blockage ());
}
-/* Emit instructions to restore register REG from slot MEM. */
+static rtx cfa_restores = NULL_RTX;
+
+/* Emit instructions to restore register REG from slot MEM. Also update
+ the cfa_restores list. */
static void
mips_restore_reg (rtx reg, rtx mem)
@@ -10238,6 +10241,7 @@ mips_restore_reg (rtx reg, rtx mem)
reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
+ cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
}
/* Emit any instructions needed before a return. */
@@ -10268,6 +10272,8 @@ mips_expand_epilogue (bool sibcall_p)
HOST_WIDE_INT step1, step2;
rtx base, target, insn;
+ cfa_restores = NULL_RTX;
+
if (!sibcall_p && mips_can_use_return_insn ())
{
emit_jump_insn (gen_return ());
@@ -10324,12 +10330,26 @@ mips_expand_epilogue (bool sibcall_p)
if (!TARGET_MIPS16)
target = stack_pointer_rtx;
- emit_insn (gen_add3_insn (target, base, adjust));
+ insn = emit_insn (gen_add3_insn (target, base, adjust));
+ if (!frame_pointer_needed && target == stack_pointer_rtx)
+ {
+ RTX_FRAME_RELATED_P (insn) = 1;
+ add_reg_note (insn, REG_CFA_DEF_CFA,
+ plus_constant (stack_pointer_rtx, step2));
+ }
}
/* Copy TARGET into the stack pointer. */
if (target != stack_pointer_rtx)
- mips_emit_move (stack_pointer_rtx, target);
+ {
+ insn = mips_emit_move (stack_pointer_rtx, target);
+ if (!frame_pointer_needed)
+ {
+ add_reg_note (insn, REG_CFA_DEF_CFA,
+ plus_constant (stack_pointer_rtx, step2));
+ RTX_FRAME_RELATED_P (insn) = 1;
+ }
+ }
/* If we're using addressing macros, $gp is implicitly used by all
SYMBOL_REFs. We must emit a blockage insn before restoring $gp
@@ -10393,9 +10413,14 @@ mips_expand_epilogue (bool sibcall_p)
/* If we don't use shoadow register set, we need to update SP. */
if (!cfun->machine->use_shadow_register_set_p && step2 > 0)
- emit_insn (gen_add3_insn (stack_pointer_rtx,
- stack_pointer_rtx,
- GEN_INT (step2)));
+ {
+ insn = emit_insn (gen_add3_insn (stack_pointer_rtx,
+ stack_pointer_rtx,
+ GEN_INT (step2)));
+ REG_NOTES (insn) = cfa_restores;
+ RTX_FRAME_RELATED_P (insn) = 1;
+ add_reg_note (insn, REG_CFA_DEF_CFA, stack_pointer_rtx);
+ }
/* Move to COP0 Status. */
emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
@@ -10405,9 +10430,14 @@ mips_expand_epilogue (bool sibcall_p)
{
/* Deallocate the final bit of the frame. */
if (step2 > 0)
- emit_insn (gen_add3_insn (stack_pointer_rtx,
- stack_pointer_rtx,
- GEN_INT (step2)));
+ {
+ insn = emit_insn (gen_add3_insn (stack_pointer_rtx,
+ stack_pointer_rtx,
+ GEN_INT (step2)));
+ REG_NOTES (insn) = cfa_restores;
+ RTX_FRAME_RELATED_P (insn) = 1;
+ add_reg_note (insn, REG_CFA_DEF_CFA, stack_pointer_rtx);
+ }
}
}
