> Note that the ADDXC, ADDXCCC, SUBXC and SUBXCCC instructions do not
    > support immediate operands.  Hence the patch breaks vis3-enabling arches
    > and niagara-7.
    Egad.  I totally overlooked this (yet the -mcpu=niagara7 -m64 testsuite is 
    rather explicit) and this is a bit of a shame, especially for SUBXC which 
    becomes less useful, you need something like:
    long foo2 (long a, long i)
      return a - (i != 0);
    to generate it:
            cmp     %g0, %o1
            jmp     %o7+8
             subxc  %o0, %g0, %o0

Yes, it is unfortunate for these instructions to not support 1,i,d

I am bringing this up with the hardware chaps to see if this could be
fixed in future revisions of the architecture.  Will keep you posted.

    > (Yes, ADXCC and SUBXCC both support immediate operands, it can be
    > confusing :/)
    The mere (re-)naming is already confusing. ;-)
    Thanks for the heads up.  I have installed the attached corrective patch.

Thanks!  I am testing it right now.

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