Re: [PATCH][rtlanal.c] Convert conditional compilation on WORD_REGISTER_OPERATIONS

[Kyrill Tkachov]

On 03/11/16 12:05, Kyrill Tkachov wrote:

On 02/11/16 11:36, Eric Botcazou wrote:

I think you're right. I suppose the new condition should be:

#ifdef LOAD_EXTEND_OP
         /* If this is a typical RISC machine, we only have to worry
            about the way loads are extended.  */
      if (!WORD_REGISTER_OPERATIONS

          || ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND

             ? val_signbit_known_set_p (inner_mode, nonzero)

             : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND)
           ||
           || !MEM_P (SUBREG_REG (x))))

#endif

Agreed.

Would you prefer me to make this change or just revert the patch?

Go ahead and make the change, but please do a bit of comment massaging in the
process, for example:

#ifdef LOAD_EXTEND_OP
           /* On many CISC machines, accessing an object in a wider mode
         causes the high-order bits to become undefined.  So they are
         not known to be zero.  */
           if (!WORD_REGISTER_OPERATIONS
         /* If this is a typical RISC machine, we only have to worry
                about the way loads are extended.  */
               || ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
                      ? val_signbit_known_set_p (inner_mode, nonzero)
                      : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND)
                    || !MEM_P (SUBREG_REG (x))))
#endif
        {
          if (GET_MODE_PRECISION (GET_MODE (x))
          > GET_MODE_PRECISION (inner_mode))
        nonzero |= (GET_MODE_MASK (GET_MODE (x))
                & ~GET_MODE_MASK (inner_mode));
        }

Thanks, here is the patch doing this.
Committing to trunk after bootstrap and testing on x86_64.

Sorry for the trouble,
Kyrill

With the following ChangeLog entry:

2016-11-03  Kyrylo Tkachov  <kyrylo.tkac...@arm.com>

    * rtlanal.c (nonzero_bits1): Fix WORD_REGISTER_OPERATIONS condition.
    Move comments into more natural position.