We transform floating point divide instructions to a faster series of
simple instructions, "swdiv".  Currently we do not do that until the
first splitter pass, which is much too late for most optimisations
that can happen on those new instructions, e.g. the constant loads
are not CSEd inside an unrolled loop.  This patch changes things so
those divide instructions are expanded during expand already.

Bootstrapped and tested on powerpc64-linux; Bill has run SPEC on it,
and if anything it shows a slight improvement.

Is this okay for trunk?


Segher


---
 gcc/config/rs6000/rs6000.md | 10 +++++++++-
 gcc/config/rs6000/vector.md | 10 +++++++++-
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index e432a5a..e08f120 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4457,7 +4457,15 @@ (define_expand "div<mode>3"
        (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
                  (match_operand:SFDF 2 "gpc_reg_operand" "")))]
   "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
-  "")
+{
+  if (RS6000_RECIP_AUTO_RE_P (<MODE>mode)
+      && can_create_pseudo_p () && flag_finite_math_only
+      && !flag_trapping_math && flag_reciprocal_math)
+    {
+      rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
+      DONE;
+    }
+})
 
 (define_insn "*div<mode>3_fpr"
   [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 7240345..05f3bdb 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -248,7 +248,15 @@ (define_expand "div<mode>3"
        (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
                   (match_operand:VEC_F 2 "vfloat_operand" "")))]
   "VECTOR_UNIT_VSX_P (<MODE>mode)"
-  "")
+{
+  if (RS6000_RECIP_AUTO_RE_P (<MODE>mode)
+      && can_create_pseudo_p () && flag_finite_math_only
+      && !flag_trapping_math && flag_reciprocal_math)
+    {
+      rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
+      DONE;
+    }
+})
 
 (define_expand "neg<mode>2"
   [(set (match_operand:VEC_F 0 "vfloat_operand" "")
-- 
1.9.3

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