Ramana Radhakrishnan wrote: > On Thu, Nov 3, 2016 at 12:20 PM, Wilco Dijkstra <wilco.dijks...@arm.com> > wrote:
> HOST_WIDE_INT val = INTVAL (index); > - /* ??? Can we assume ldrd for thumb2? */ > - /* Thumb-2 ldrd only has reg+const addressing modes. */ > - /* ldrd supports offsets of +-1020. > - However the ldr fallback does not. */ > - return val > -256 && val < 256 && (val & 3) == 0; > + /* Thumb-2 ldrd only has reg+const addressing modes. > + Assume we emit ldrd or 2x ldr if !TARGET_LDRD. > + If vldr is selected it uses arm_coproc_mem_operand. */ > + if (TARGET_LDRD) > I suspect this should be : if (TARGET_LDRD && !fix_cm3_ldrd) - I am a > bit worried about this change because of the non-uniformity with ldr > and the fallout with other places where things may break with this. I > would like a test with -mcpu=cortex-m3/-mthumb as well for an > arm-none-eabi target to see what the fallout of this change is on that Well it works fine given that Thumb-2 supports add/sub up to 4KB, so the existing expansion into add+ldrd for the fix_cm3_ldrd case works fine. I ran a bootstrap with fix_cm3_ldrd forced to true, and that completed without any issues. Wilco
