On Thu, Nov 17, 2016 at 04:53:03PM +0100, Dominik Vogt wrote:
> The following two patches fix PR 77822 on s390x for gcc-7. As the
> macro doing the argument range checks can be used on other targets
> as well, I've put it in system.h (couldn't think of a better
> place; maybe rtl.h?).
>
> Bootstrapped on s390x biarch, regression tested on s390x biarch
> and s390, all on a zEC12 with -march=zEC12.
>
> Please check the commit messages for details.
S390 backend patch.
Ciao
Dominik ^_^ ^_^
--
Dominik Vogt
IBM Germany
gcc/ChangeLog
* config/s390/s390.md ("extzv")
("*extzv<mode><clobbercc_or_nocc>")
("*extzvdi<clobbercc_or_nocc>_lshiftrt")
("*<risbg_n>_ior_and_sr_ze")
("*extract1bitdi<clobbercc_or_nocc>")
("*insv<mode><clobbercc_or_nocc>", "*insv_rnsbg_noshift")
("*insv_rnsbg_srl", "*insv<mode>_mem_reg")
("*insvdi_mem_reghigh", "*insvdi_reg_imm"): Use SIZE_POS_IN_RANGE to
validate the arguments of zero_extract and sign_extract.
>From 2e20be51e86cde2e02f8f02e0367456d3fe8d92b Mon Sep 17 00:00:00 2001
From: Dominik Vogt <v...@linux.vnet.ibm.com>
Date: Thu, 17 Nov 2016 14:49:48 +0100
Subject: [PATCH 2/2] PR target/77822: S390: Validate argument range of
{zero,sign}_extract.
With some undefined code, combine generates patterns where the arguments to
*_extract are out of range, e.b. a negative bit position. If the s390 backend
accepts these, they lead to not just undefined behaviour but invalid assembly
instructions (argument out of the allowed range). So this patch makes sure
that the rtl expressions with out of range arguments are rejected.
---
gcc/config/s390/s390.md | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index fedd6f9..d2dfb1e 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -3741,6 +3741,8 @@
(clobber (reg:CC CC_REGNUM))])]
"TARGET_Z10"
{
+ if (! SIZE_POS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64))
+ FAIL;
/* Starting with zEC12 there is risbgn not clobbering CC. */
if (TARGET_ZEC12)
{
@@ -3760,7 +3762,9 @@
(match_operand 2 "const_int_operand" "") ; size
(match_operand 3 "const_int_operand" ""))) ; start
]
- "<z10_or_zEC12_cond>"
+ "<z10_or_zEC12_cond>
+ && SIZE_POS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]),
+ GET_MODE_BITSIZE (<MODE>mode))"
"<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end,
shift
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
@@ -3773,6 +3777,7 @@
(lshiftrt:DI (match_operand:DI 3 "register_operand" "d")
(match_operand:DI 4 "nonzero_shift_count_operand" "")))]
"<z10_or_zEC12_cond>
+ && SIZE_POS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
&& 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])"
"<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4"
[(set_attr "op_type" "RIE")
@@ -3791,6 +3796,7 @@
(match_operand 5 "const_int_operand" "")) ; start
4)))]
"<z10_or_zEC12_cond>
+ && SIZE_POS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64)
&& UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))"
"<risbg_n>\t%0,%3,64-%4,63,%4+%5"
[(set_attr "op_type" "RIE")
@@ -3804,7 +3810,8 @@
(const_int 1) ; size
(match_operand 2 "const_int_operand" "")) ; start
(const_int 0)))]
- "<z10_or_zEC12_cond>"
+ "<z10_or_zEC12_cond>
+ && SIZE_POS_IN_RANGE (1, INTVAL (operands[2]), 64)"
"<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
@@ -3919,6 +3926,8 @@
(match_operand 2 "const_int_operand" "I")) ; pos
(match_operand:GPR 3 "nonimmediate_operand" "d"))]
"<z10_or_zEC12_cond>
+ && SIZE_POS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]),
+ GET_MODE_BITSIZE (<MODE>mode))
&& (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
"<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1"
[(set_attr "op_type" "RIE")
@@ -4214,6 +4223,7 @@
(match_operand:DI 3 "nonimmediate_operand" "d")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10
+ && SIZE_POS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
&& INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
"rnsbg\t%0,%3,%2,63,0"
[(set_attr "op_type" "RIE")])
@@ -4230,6 +4240,7 @@
(match_operand:DI 4 "nonimmediate_operand" "d")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10
+ && SIZE_POS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
&& INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
"rnsbg\t%0,%4,%2,%2+%1-1,%3"
[(set_attr "op_type" "RIE")])
@@ -4239,7 +4250,8 @@
(match_operand 1 "const_int_operand" "n,n")
(const_int 0))
(match_operand:W 2 "register_operand" "d,d"))]
- "INTVAL (operands[1]) > 0
+ "SIZE_POS_IN_RANGE (INTVAL (operands[1]), 0, 64)
+ && INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
{
@@ -4260,6 +4272,7 @@
(lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
(const_int 32)))]
"TARGET_ZARCH
+ && SIZE_POS_IN_RANGE (INTVAL (operands[1]), 0, 64)
&& INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
@@ -4278,6 +4291,7 @@
(match_operand 1 "const_int_operand" "n"))
(match_operand:DI 2 "const_int_operand" "n"))]
"TARGET_ZARCH
+ && SIZE_POS_IN_RANGE (16, INTVAL (operands[1]), 64)
&& INTVAL (operands[1]) >= 0
&& INTVAL (operands[1]) < BITS_PER_WORD
&& INTVAL (operands[1]) % 16 == 0"
--
2.3.0
