> Actually, thinking more about it: the assumption we're making in the > WORDS_BIG_ENDIAN != REG_WORDS_BIG_ENDIAN condition discussed below is > really: > > /* We assume that the ordering of registers within a multi-register > value has a consistent endianness: if bytes and register words > have different endianness, the hard registers that make up a > multi-register value must be at least word-sized. */ > > (quoted from the revised patch below). And with that assumption this > check is simply REG_WORDS_BIG_ENDIAN vs. !REG_WORDS_BIG_ENDIAN.
In other words, this would break for an architecture with subword-sized registers and different byte endianness and register word endianness. > (I've checked ports for mixed byte/word endianness (think that's > just pdp11) and word/reg-word endianness (think that's just c6x), > and the assumption does seem to hold. I'd be very surprised if we > coped correctly with more exotic combinations, including for the > reasons quoted below.) That seems sensible to me. > 2016-11-15 Richard Sandiford <richard.sandif...@arm.com> > Alan Hayward <alan.hayw...@arm.com> > David Sherwood <david.sherw...@arm.com> > > * rtlanal.c (subreg_get_info): Use more local variables. > Remark that for HARD_REGNO_NREGS_HAS_PADDING, each scalar unit > occupies at least one register. Assume that full hard registers > have consistent endianness. Share previously-duplicated if block. > Rework the main handling so that it operates on independently- > addressable YMODE-sized blocks. Use subreg_size_lowpart_offset > to check lowpart offsets, without trying to find an equivalent > integer mode first. Handle WORDS_BIG_ENDIAN != REG_WORDS_BIG_ENDIAN > as a final register-endianness correction. OK, thanks. -- Eric Botcazou
