By this patch, I add a build-time option ` --with-unfused-madd4=yes/no’,
and runtime option -m(no-)unfused-madd4,
to disable generate madd.fmt instructions.
These 2 options is needed due to madd.fmt/msub.fmt on Loongson are broken,
which may generate wrong calculator result.
diff --git a/src/gcc/config.gcc b/src/gcc/config.gcc
index 1b7da0e..3a30b44 100644
--- a/src/gcc/config.gcc
+++ b/src/gcc/config.gcc
@@ -3991,7 +3991,7 @@ case "${target}" in
;;
mips*-*-*)
- supported_defaults="abi arch arch_32 arch_64 float fpu nan
fp_32 odd_spreg_32 tune tune_32 tune_64 divide llsc mips-plt synci"
+ supported_defaults="abi arch arch_32 arch_64 float fpu nan
fp_32 odd_spreg_32 unfused_madd4 tune tune_32 tune_64 divide llsc mips-plt
synci"
case ${with_float} in
"" | soft | hard)
@@ -4048,6 +4048,19 @@ case "${target}" in
exit 1
;;
esac
+
+ case ${with_unfused_madd4} in
+ "" | yes)
+ with_unfused_madd4="unfused-madd4"
+ ;;
+ no)
+ with_unfused_madd4="no-unfused-madd4"
+ ;;
+ *)
+ echo "Unknown unfused_madd4 type used in
--with-unfused-madd4=$with_unfused_madd4" 1>&2
+ exit 1
+ ;;
+ esac
case ${with_abi} in
"" | 32 | o64 | n32 | 64 | eabi)
@@ -4547,7 +4560,7 @@ case ${target} in
esac
t=
-all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64
schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls"
+all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64
schedule float mode fpu nan fp_32 odd_spreg_32 unfused_madd4 divide llsc
mips-plt synci tls"
for option in $all_defaults
do
eval "val=\$with_"`echo $option | sed s/-/_/g`
diff --git a/src/gcc/config/mips/mips.c b/src/gcc/config/mips/mips.c
index 5af3d1e..236ab94 100644
--- a/src/gcc/config/mips/mips.c
+++ b/src/gcc/config/mips/mips.c
@@ -17992,6 +17992,16 @@ mips_option_override (void)
will be produced. */
target_flags |= MASK_ODD_SPREG;
}
+
+ /* If neither -munfused-madd nor -mno-unfused-madd was given on the command
+ line, set MASK_UNFSUED_MADD based on the ISA. */
+ if ((target_flags_explicit & MASK_UNFUSED_MADD4) == 0)
+ {
+ if (!ISA_HAS_UNFUSED_MADD4)
+ target_flags &= ~MASK_UNFUSED_MADD4;
+ else
+ target_flags |= MASK_UNFUSED_MADD4;
+ }
if (!ISA_HAS_COMPACT_BRANCHES && mips_cb == MIPS_CB_ALWAYS)
{
diff --git a/src/gcc/config/mips/mips.h b/src/gcc/config/mips/mips.h
index 763ca58..8c7d24e 100644
--- a/src/gcc/config/mips/mips.h
+++ b/src/gcc/config/mips/mips.h
@@ -892,6 +892,7 @@ struct mips_cpu_info {
":%{!msoft-float:%{!msingle-float:%{!mfp*:-mfp%(VALUE)}}}}" }, \
{"odd_spreg_32", "%{" OPT_ARCH32 ":%{!msoft-float:%{!msingle-float:" \
"%{!modd-spreg:%{!mno-odd-spreg:-m%(VALUE)}}}}}" }, \
+ {"unfused_madd4", "%{!munfused-madd4:%{!mno-unfused-madd4:-m%(VALUE)}}" }, \
{"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
{"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
{"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
@@ -1089,7 +1090,7 @@ struct mips_cpu_info {
/* ISA has 4 operand unfused madd instructions of the form
'd = [+-] (a * b [+-] c)'. */
-#define ISA_HAS_UNFUSED_MADD4 (ISA_HAS_FP4 && !TARGET_MIPS8000)
+#define ISA_HAS_UNFUSED_MADD4 (ISA_HAS_FP4 && !TARGET_MIPS8000 &&
TARGET_UNFUSED_MADD4)
/* ISA has 3 operand r6 fused madd instructions of the form
'c = c [+-] (a * b)'. */
diff --git a/src/gcc/config/mips/mips.opt b/src/gcc/config/mips/mips.opt
index ebd67e4..a8c23f6 100644
--- a/src/gcc/config/mips/mips.opt
+++ b/src/gcc/config/mips/mips.opt
@@ -412,6 +412,10 @@ modd-spreg
Target Report Mask(ODD_SPREG)
Enable use of odd-numbered single-precision registers.
+munfused-madd4
+Target Report Mask(UNFUSED_MADD4)
+Enable unfused multiply-add/multiply-sub instruction, aka madd.fmt/msub.fmt.
+
mframe-header-opt
Target Report Var(flag_frame_header_optimization) Optimization
Optimize frame header.
