From 1fd1c89a7fc9c9df78a5e5c16746d3cd901e5bf9 Mon Sep 17 00:00:00 2001 From: "julia.koval" Date: Wed, 21 Dec 2016 10:49:53 +0300 Subject: [PATCH] Enable SGX --- gcc/common/config/i386/i386-common.c | 15 +++ gcc/config.gcc | 6 +- gcc/config/i386/cpuid.h | 1 + gcc/config/i386/driver-i386.c | 6 +- gcc/config/i386/i386-c.c | 2 + gcc/config/i386/i386.c | 6 ++ gcc/config/i386/i386.h | 2 + gcc/config/i386/i386.opt | 4 + gcc/config/i386/sgxintrin.h | 177 +++++++++++++++++++++++++++++++++++ gcc/config/i386/x86intrin.h | 2 + gcc/testsuite/gcc.target/i386/sgx.c | 24 +++++ libgcc/config/i386/cpuinfo.c | 2 + libgcc/config/i386/cpuinfo.h | 1 + 13 files changed, 244 insertions(+), 4 deletions(-) create mode 100644 gcc/config/i386/sgxintrin.h create mode 100644 gcc/testsuite/gcc.target/i386/sgx.c diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index 98224f5..8aab0af 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -115,6 +115,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_ABM_SET \ (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT) +#define OPTION_MASK_ISA_SGX_SET OPTION_MASK_ISA_SGX #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT @@ -212,6 +213,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM +#define OPTION_MASK_ISA_SGX_UNSET OPTION_MASK_ISA_SGX #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT @@ -481,6 +483,19 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_msgx: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_SGX_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_UNSET; + } + return true; + case OPT_mavx512dq: if (value) { diff --git a/gcc/config.gcc b/gcc/config.gcc index 7afbc54..d4cb6db 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -375,7 +375,8 @@ i[34567]86-*-*) avx512vlintrin.h avx512vlbwintrin.h avx512vldqintrin.h avx512ifmaintrin.h avx512ifmavlintrin.h avx512vbmiintrin.h avx512vbmivlintrin.h avx5124fmapsintrin.h avx5124vnniwintrin.h - clwbintrin.h mwaitxintrin.h clzerointrin.h pkuintrin.h" + clwbintrin.h mwaitxintrin.h clzerointrin.h pkuintrin.h + sgxintrin.h" ;; x86_64-*-*) cpu_type=i386 @@ -397,7 +398,8 @@ x86_64-*-*) avx512vlintrin.h avx512vlbwintrin.h avx512vldqintrin.h avx512ifmaintrin.h avx512ifmavlintrin.h avx512vbmiintrin.h avx512vbmivlintrin.h avx5124fmapsintrin.h avx5124vnniwintrin.h - clwbintrin.h mwaitxintrin.h clzerointrin.h pkuintrin.h" + clwbintrin.h mwaitxintrin.h clzerointrin.h pkuintrin.h + sgxintrin.h" ;; ia64-*-*) extra_headers=ia64intrin.h diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index abe7c62..f9e4f8e 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -73,6 +73,7 @@ /* Extended Features (%eax == 7) */ /* %ebx */ #define bit_FSGSBASE (1 << 0) +#define bit_SGX (1 << 2) #define bit_BMI (1 << 3) #define bit_HLE (1 << 4) #define bit_AVX2 (1 << 5) diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index f0d0e8f..0cb80d0 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -404,7 +404,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0; unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0; unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0; - unsigned int has_hle = 0, has_rtm = 0; + unsigned int has_hle = 0, has_rtm = 0, has_sgx = 0; unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0; unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0; unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0; @@ -480,6 +480,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) __cpuid_count (7, 0, eax, ebx, ecx, edx); has_bmi = ebx & bit_BMI; + has_sgx = ebx & bit_SGX; has_hle = ebx & bit_HLE; has_rtm = ebx & bit_RTM; has_avx2 = ebx & bit_AVX2; @@ -993,6 +994,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4"; const char *xop = has_xop ? " -mxop" : " -mno-xop"; const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi"; + const char *sgx = has_sgx ? " -msgx" : " -mno-sgx"; const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2"; const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm"; const char *avx = has_avx ? " -mavx" : " -mno-avx"; @@ -1032,7 +1034,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) const char *pku = has_pku ? " -mpku" : " -mno-pku"; options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3, sse4a, cx16, sahf, movbe, aes, sha, pclmul, - popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2, + popcnt, abm, lwp, fma, fma4, xop, bmi, sgx, bmi2, tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm, hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx, fxsr, xsave, xsaveopt, avx512f, avx512er, diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 6e56c83..31beb3b 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -378,6 +378,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__AVX512IFMA__"); if (isa_flag2 & OPTION_MASK_ISA_AVX5124VNNIW) def_or_undef (parse_in, "__AVX5124VNNIW__"); + if (isa_flag2 & OPTION_MASK_ISA_SGX) + def_or_undef (parse_in, "__SGX__"); if (isa_flag2 & OPTION_MASK_ISA_AVX5124FMAPS) def_or_undef (parse_in, "__AVX5124FMAPS__"); if (isa_flag & OPTION_MASK_ISA_FMA) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 624f069..e2722a9 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -4320,6 +4320,7 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_INT isa2, int flags, { { "-mavx5124vnniw", OPTION_MASK_ISA_AVX5124VNNIW }, { "-mavx5124fmaps", OPTION_MASK_ISA_AVX5124FMAPS }, + { "-msgx", OPTION_MASK_ISA_SGX }, }; /* Flag options. */ static struct ix86_target_opts flag_opts[] = @@ -4919,6 +4920,7 @@ ix86_option_override_internal (bool main_args_p, #define PTA_PKU (HOST_WIDE_INT_1 << 59) #define PTA_AVX5124VNNIW (HOST_WIDE_INT_1 << 60) #define PTA_AVX5124FMAPS (HOST_WIDE_INT_1 << 61) +#define PTA_SGX (HOST_WIDE_INT_1 << 62) #define PTA_CORE2 \ (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \ @@ -5581,6 +5583,9 @@ ix86_option_override_internal (bool main_args_p, if (processor_alias_table[i].flags & PTA_AVX5124FMAPS && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_AVX5124FMAPS)) opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS; + if (processor_alias_table[i].flags & PTA_SGX + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX; if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)) x86_prefetch_sse = true; @@ -6608,6 +6613,7 @@ ix86_valid_target_attribute_inner_p (tree args, char *p_strings[], /* isa options */ IX86_ATTR_ISA ("3dnow", OPT_m3dnow), IX86_ATTR_ISA ("abm", OPT_mabm), + IX86_ATTR_ISA ("sgx", OPT_msgx), IX86_ATTR_ISA ("bmi", OPT_mbmi), IX86_ATTR_ISA ("bmi2", OPT_mbmi2), IX86_ATTR_ISA ("lzcnt", OPT_mlzcnt), diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 5f5368d..ff69b79 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -98,6 +98,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_ROUND TARGET_ISA_ROUND #define TARGET_ABM TARGET_ISA_ABM #define TARGET_ABM_P(x) TARGET_ISA_ABM_P(x) +#define TARGET_SGX TARGET_ISA_SGX +#define TARGET_SGX_P(x) TARGET_ISA_SGX_P(x) #define TARGET_BMI TARGET_ISA_BMI #define TARGET_BMI_P(x) TARGET_ISA_BMI_P(x) #define TARGET_BMI2 TARGET_ISA_BMI2 diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 390412a..10b1e0f 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -733,6 +733,10 @@ mpopcnt Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save Support code generation of popcnt instruction. +msgx +Target Report Mask(ISA_SGX) Var(ix86_isa_flags) Save +Support SGX built-in functions and code generation. + mbmi Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save Support BMI built-in functions and code generation. diff --git a/gcc/config/i386/sgxintrin.h b/gcc/config/i386/sgxintrin.h new file mode 100644 index 0000000..f6eb937 --- /dev/null +++ b/gcc/config/i386/sgxintrin.h @@ -0,0 +1,177 @@ +#ifndef _SGXINTRIN_H_INCLUDED +#define _SGXINTRIN_H_INCLUDED + +#ifndef __SGX__ +#pragma GCC push_options +#pragma GCC target("sgx") +#define __DISABLE_SGX__ +#endif /* __SGX__ */ + +#define __encls_bc(leaf, b, c, retval) \ + __asm__ __volatile__ ("encls\n\t" \ + : "=a" (retval) \ + : "a" (leaf), "b" (b), "c" (c) \ + : "cc") + +#define __encls_bcd(leaf, b, c, d, retval) \ + __asm__ __volatile__("encls\n\t" \ + : "=a" (retval) \ + : "a" (leaf), "b" (b), "c" (c), "d" (d) \ + : "cc") + +#define __encls_c(leaf, c, retval) \ + __asm__ __volatile__("encls\n\t" \ + : "=a" (retval) \ + : "a" (leaf), "c" (c) \ + : "cc") + +#define __encls_edbgrd(leaf, b, c, retval) \ + __asm__ __volatile__("encls\n\t" \ + : "=a" (retval), "=b" (b) \ + : "a" (leaf), "c" (c)) + +#define __encls_generic(leaf, b, c, d, retval) \ + __asm__ __volatile__("encls\n\t" \ + : "=a" (retval), "=b" (b), "=c" (c), "=d" (d)\ + : "a" (leaf), "b" (b), "c" (c), "d" (d) \ + : "cc") + +#define __enclu_bc(leaf, b, c, retval) \ + __asm__ __volatile__("enclu\n\t" \ + : "=a" (retval) \ + : "a" (leaf), "b" (b), "c" (c) \ + : "cc") + +#define __enclu_bcd(leaf, b, c, d, retval) \ + __asm__ __volatile__("enclu\n\t" \ + : "=a" (retval) \ + : "a" (leaf), "b" (b), "c" (c), "d" (d) \ + : "cc") + +#define __enclu_eenter(leaf, b, c, retval) \ + __asm__ __volatile__("enclu\n\t" \ + : "=a" (retval), "=c" (c) \ + : "a" (leaf), "b" (b), "c" (c) \ + : "cc") + +#define __enclu_eexit(leaf, b, c, retval) \ + __asm__ __volatile__("enclu\n\t" \ + : "=a" (retval), "=c" (c) \ + : "a" (leaf), "b" (b) \ + : "cc") + +#define __enclu_generic(leaf, b, c, d, retval) \ + __asm__ __volatile__("enclu\n\t" \ + : "=a" (retval), "=b" (b), "=c" (c), "=d" (d)\ + : "a" (leaf), "b" (b), "c" (c), "d" (d) \ + : "cc") + + +extern __inline int +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_encls_u32 (const int __L, size_t *__D) +{ + enum __encls_type + { + __SGX_ECREATE = 0x00, + __SGX_EADD = 0x01, + __SGX_EINIT = 0x02, + __SGX_EREMOVE = 0x03, + __SGX_EDBGRD = 0x04, + __SGX_EDBGWR = 0x05, + __SGX_EEXTEND = 0x06, + __SGX_ELDB = 0x07, + __SGX_ELDU = 0x08, + __SGX_EBLOCK = 0x09, + __SGX_EPA = 0x0A, + __SGX_EWB = 0x0B, + __SGX_ETRACK = 0x0C, + __SGX_EAUG = 0x0D, + __SGX_EMODPR = 0x0E, + __SGX_EMODT = 0x0F + }; + enum __encls_type __T = (enum __encls_type)__L; + int __R = 0; + if (!__builtin_constant_p (__T)) + __encls_generic (__L, __D[0], __D[1], __D[2], __R); + else switch (__T) + { + case __SGX_ECREATE: + case __SGX_EADD: + case __SGX_EDBGWR: + case __SGX_EEXTEND: + case __SGX_EPA: + case __SGX_EMODPR: + case __SGX_EMODT: + case __SGX_EAUG: + __encls_bc (__L, __D[0], __D[1], __R); + break; + case __SGX_EINIT: + case __SGX_ELDB: + case __SGX_ELDU: + case __SGX_EWB: + __encls_bcd (__L, __D[0], __D[1], __D[2], __R); + break; + case __SGX_EREMOVE: + case __SGX_EBLOCK: + case __SGX_ETRACK: + __encls_c (__L, __D[1], __R); + break; + case __SGX_EDBGRD: + __encls_edbgrd (__L, __D[0], __D[1], __R); + break; + default: + return -1; + } + return __R; +} + +extern __inline int +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_enclu_u32 (const int __L, size_t *__D) +{ + enum __enclu_type + { + __SGX_EREPORT = 0x00, + __SGX_EGETKEY = 0x01, + __SGX_EENTER = 0x02, + __SGX_ERESUME = 0x03, + __SGX_EEXIT = 0x04, + __SGX_EACCEPT = 0x05, + __SGX_EMODPE = 0x06, + __SGX_EACCEPTCOPY = 0x07 + }; + enum __enclu_type __T = (enum __enclu_type) __L; + int __R = 0; + if (!__builtin_constant_p (__T)) + __enclu_generic (__L, __D[0], __D[1], __D[2], __R); + else switch (__T) + { + case __SGX_EREPORT: + case __SGX_EACCEPTCOPY: + __enclu_bcd (__L, __D[0], __D[1], __D[2], __R); + break; + case __SGX_EGETKEY: + case __SGX_ERESUME: + case __SGX_EACCEPT: + case __SGX_EMODPE: + __enclu_bc (__L, __D[0], __D[1], __R); + break; + case __SGX_EENTER: + __enclu_eenter (__L, __D[0], __D[1], __R); + break; + case __SGX_EEXIT: + __enclu_eexit (__L, __D[0], __D[1], __R); + break; + default: + return -1; + } + return __R; +} + +#ifdef __DISABLE_SGX__ +#undef __DISABLE_SGX__ +#pragma GCC pop_options +#endif /* __DISABLE_SGX__ */ + +#endif /* _SGXINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/x86intrin.h b/gcc/config/i386/x86intrin.h index ee5c38a..ab0be21 100644 --- a/gcc/config/i386/x86intrin.h +++ b/gcc/config/i386/x86intrin.h @@ -75,6 +75,8 @@ #include +#include + #endif /* __iamcu__ */ #include diff --git a/gcc/testsuite/gcc.target/i386/sgx.c b/gcc/testsuite/gcc.target/i386/sgx.c new file mode 100644 index 0000000..42ad1fc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sgx.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msgx" } */ +/* { dg-final { scan-assembler-times "enclu" 2 } } */ +/* { dg-final { scan-assembler-times "encls" 2 } } */ + +#include + +extern int leaf; + +#define SGX_EENTER 0x02 +#define SGX_EBLOCK 0x09 + +int foo () +{ + size_t test[3]; + test[0] = 4; + test[1] = 5; + test[2] = 6; + int res1 = _encls_u32 (leaf, test); + int res2 = _enclu_u32 (leaf, test); + int res3 = _encls_u32 (SGX_EBLOCK, test); + int res4 = _enclu_u32 (SGX_EENTER, test); + return 0; +} diff --git a/libgcc/config/i386/cpuinfo.c b/libgcc/config/i386/cpuinfo.c index 9f30cb8..2475ba8 100644 --- a/libgcc/config/i386/cpuinfo.c +++ b/libgcc/config/i386/cpuinfo.c @@ -251,6 +251,8 @@ get_available_features (unsigned int ecx, unsigned int edx, __cpuid_count (7, 0, eax, ebx, ecx, edx); if (ebx & bit_BMI) features |= (1 << FEATURE_BMI); + if (ebx & bit_SGX) + features |= (1 << FEATURE_SGX); if (ebx & bit_AVX2) features |= (1 << FEATURE_AVX2); if (ebx & bit_BMI2) diff --git a/libgcc/config/i386/cpuinfo.h b/libgcc/config/i386/cpuinfo.h index cf848e6..cb4acb5 100644 --- a/libgcc/config/i386/cpuinfo.h +++ b/libgcc/config/i386/cpuinfo.h @@ -92,6 +92,7 @@ enum processor_features FEATURE_FMA, FEATURE_AVX512F, FEATURE_BMI, + FEATURE_SGX, FEATURE_BMI2, FEATURE_AES, FEATURE_PCLMUL, -- 2.5.5