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  <h3>IA-32/x86-64</h3>
    <ul>
+     <li>Support for Intel AVX2 intrinsics, built-in functions and code generation is
+ 	available via <code>-mavx2</code>.</li>
+     <li>Support for Intel BMI2 intrinsics, built-in functions and code generation is
+ 	available via <code>-mbmi2</code>.</li>
+     <li>Implementation and automatic generation of <code>__builtin_clz*</code> 
+       using <code>lzcnt</code> instruction is available via <code>-mlzcnt</code>.</li>
+     <li>Support for Intel FMA3 intrinsics and code generation is available via
+       <code>-mfma</code>.</li>
+     <li>A new <code>-mfsgsbase</code> option is available to enable GCC
+     to use new segment register read/write instructions through dedicated built-ins.</li>
+     <li>Support for new Intel <code>rdrnd</code> instruction is available via <code>-mrdrnd</code>.</li>
+     <li>Two additional AVX vector conversion instructions are available via <code>-mf16c</code>.</li>
+     <li>Support for new Intel processor codename IvyBridge with RDRND, FSGSBASE and F16C
+       is available through <code>-march=core-avx-i</code>.
+     <li>Support for new Intel processor codename Haswell with AVX2, FMA, BMI,
+       BMI2, LZCNT is available through <code>-march=core-avx2</code>.
      <li>...</li>
    </ul>